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Groups > linux.kernel > #1254785
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI |
| Date | 2015-10-23 20:10 +0200 |
| Message-ID | <qmOWR-DI-9@gated-at.bofh.it> (permalink) |
| References | (3 earlier) <qmjzI-5kR-11@gated-at.bofh.it> <qmjJn-5wE-15@gated-at.bofh.it> <qmjT4-5Ic-13@gated-at.bofh.it> <qmkcp-6lH-11@gated-at.bofh.it> <qmmHg-1w5-11@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
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On Thu, Oct 22, 2015 at 01:30:42PM +0200, Jens Kuske wrote: > On 22/10/15 11:14, Maxime Ripard wrote: > > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > >> On Thu, 22 Oct 2015 10:47:35 +0200 > >> Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > >> > >>> Not really. The uart0 reset is the bit 16, in the reset register 4. > >>> > >>> 4 * 32 + 16 = 44. > >>> > >>> Not 112, but still not 208 either. > >> > >> The registers are numbered 1..5, then > >> > >> (4 - 1) * 32 + 16 = 112 > > > > Not on my version, and even then, UARTs are on the last reset > > register, which would still make 144. > > > > Maxime > > > > There are holes between reg2 and reg3 and reg4 for some reason, but even > if we would correct that with some of_xlate() function they won't > completely line up with the gates. Indeed. Still, dealing with the holes and sticking to what the datasheet says seems like the right solution. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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[PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske <jenskuske@gmail.com> - 2015-10-21 18:30 +0200
[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske <jenskuske@gmail.com> - 2015-10-21 18:30 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-22 10:10 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jean-Francois Moine <moinejf@free.fr> - 2015-10-22 10:40 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-22 10:50 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jean-Francois Moine <moinejf@free.fr> - 2015-10-22 11:00 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-22 11:20 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jens Kuske <jenskuske@gmail.com> - 2015-10-22 14:00 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-23 20:10 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jean-Francois Moine <moinejf@free.fr> - 2015-10-22 19:40 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-23 20:20 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jean-Francois Moine <moinejf@free.fr> - 2015-10-23 21:30 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-24 09:20 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Jean-Francois Moine <moinejf@free.fr> - 2015-10-24 10:50 +0200
Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-26 22:10 +0100
Re: [linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Hans de Goede <hdegoede@redhat.com> - 2015-10-27 09:20 +0100
Re: [linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Hans de Goede <hdegoede@redhat.com> - 2015-10-24 10:50 +0200
Re: [linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-26 22:10 +0100
Re: [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-22 10:00 +0200
Re: [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets Jens Kuske <jenskuske@gmail.com> - 2015-10-27 18:00 +0100
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