[PATCH 0/3] pinctrl: Add support for Intel Broxton SoC

From	Mika Westerberg <mika.westerberg@linux.intel.com>
Newsgroups	linux.kernel
Subject	[PATCH 0/3] pinctrl: Add support for Intel Broxton SoC
Date	2015-10-21 12:10 +0200
Message-ID	<qlYvg-8ai-3@gated-at.bofh.it> (permalink)
Organization	linux.* mail to news gateway

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Hi,

This series adds pinctrl/GPIO support for Intel Broxton SoC. The GPIO
hardware is based on the same design already found in Intel Skylake
(Sunrisepoint PCH).

This series adds a new driver pinctrl-broxton.c which reuses the existing
Intel pinctrl core functionality and provides Broxton specific pin
configuration.

Mika Westerberg (3):
  pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt
  pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs
  pinctrl: intel: Add Intel Broxton pin controller support

 drivers/pinctrl/intel/Kconfig           |    8 +
 drivers/pinctrl/intel/Makefile          |    1 +
 drivers/pinctrl/intel/pinctrl-broxton.c | 1065 +++++++++++++++++++++++++++++++
 drivers/pinctrl/intel/pinctrl-intel.c   |   68 +-
 4 files changed, 1123 insertions(+), 19 deletions(-)
 create mode 100644 drivers/pinctrl/intel/pinctrl-broxton.c

-- 
2.6.1

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[PATCH 0/3] pinctrl: Add support for Intel Broxton SoC Mika Westerberg <mika.westerberg@linux.intel.com> - 2015-10-21 12:10 +0200
  [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt Mika Westerberg <mika.westerberg@linux.intel.com> - 2015-10-21 12:20 +0200
    Re: [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips  sharing the interrupt Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 13:40 +0100
  Re: [PATCH 3/3] pinctrl: intel: Add Intel Broxton pin controller support Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 13:40 +0100

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