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[PATCH 0/3] pinctrl: Add support for Intel Broxton SoC

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  [PATCH 0/3] pinctrl: Add support for Intel Broxton SoC Mika Westerberg <mika.westerberg@linux.intel.com> - 2015-10-21 12:10 +0200
    [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt Mika Westerberg <mika.westerberg@linux.intel.com> - 2015-10-21 12:20 +0200
      Re: [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips  sharing the interrupt Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 13:40 +0100
    Re: [PATCH 3/3] pinctrl: intel: Add Intel Broxton pin controller support Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 13:40 +0100

#1252653 — [PATCH 0/3] pinctrl: Add support for Intel Broxton SoC

Hi,

This series adds pinctrl/GPIO support for Intel Broxton SoC. The GPIO
hardware is based on the same design already found in Intel Skylake
(Sunrisepoint PCH).

This series adds a new driver pinctrl-broxton.c which reuses the existing
Intel pinctrl core functionality and provides Broxton specific pin
configuration.

Mika Westerberg (3):
  pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt
  pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs
  pinctrl: intel: Add Intel Broxton pin controller support

 drivers/pinctrl/intel/Kconfig           |    8 +
 drivers/pinctrl/intel/Makefile          |    1 +
 drivers/pinctrl/intel/pinctrl-broxton.c | 1065 +++++++++++++++++++++++++++++++
 drivers/pinctrl/intel/pinctrl-intel.c   |   68 +-
 4 files changed, 1123 insertions(+), 19 deletions(-)
 create mode 100644 drivers/pinctrl/intel/pinctrl-broxton.c

-- 
2.6.1

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#1252676 — [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt

On Intel Broxton the GPIO hardware consists of several chips that all share
the parent interrupt. It is not possible to handle this by setting chained
handler for each chip (as they will overwrite each other).

To overcome this we need to request the interrupt using devm_request_irq()
and pass IRQF_SHARED with the flags.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-intel.c | 52 +++++++++++++++++++++++++----------
 1 file changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 54848b8decef..53e9ababdb95 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/acpi.h>
 #include <linux/gpio.h>
 #include <linux/gpio/driver.h>
@@ -803,9 +804,11 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
 	return 0;
 }
 
-static void intel_gpio_community_irq_handler(struct gpio_chip *gc,
+static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
 	const struct intel_community *community)
 {
+	struct gpio_chip *gc = &pctrl->chip;
+	irqreturn_t ret = IRQ_NONE;
 	int gpp;
 
 	for (gpp = 0; gpp < community->ngpps; gpp++) {
@@ -832,24 +835,28 @@ static void intel_gpio_community_irq_handler(struct gpio_chip *gc,
 			irq = irq_find_mapping(gc->irqdomain,
 					       community->pin_base + padno);
 			generic_handle_irq(irq);
+
+			ret |= IRQ_HANDLED;
 		}
 	}
+
+	return ret;
 }
 
-static void intel_gpio_irq_handler(struct irq_desc *desc)
+static irqreturn_t intel_gpio_irq(int irq, void *data)
 {
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-	struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
-	struct irq_chip *chip = irq_desc_get_chip(desc);
+	const struct intel_community *community;
+	struct intel_pinctrl *pctrl = data;
+	irqreturn_t ret = IRQ_NONE;
 	int i;
 
-	chained_irq_enter(chip, desc);
-
 	/* Need to check all communities for pending interrupts */
-	for (i = 0; i < pctrl->ncommunities; i++)
-		intel_gpio_community_irq_handler(gc, &pctrl->communities[i]);
+	for (i = 0; i < pctrl->ncommunities; i++) {
+		community = &pctrl->communities[i];
+		ret |= intel_gpio_community_irq_handler(pctrl, community);
+	}
 
-	chained_irq_exit(chip, desc);
+	return ret;
 }
 
 static struct irq_chip intel_gpio_irqchip = {
@@ -902,21 +909,36 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
 				     0, 0, pctrl->soc->npins);
 	if (ret) {
 		dev_err(pctrl->dev, "failed to add GPIO pin range\n");
-		gpiochip_remove(&pctrl->chip);
-		return ret;
+		goto fail;
+	}
+
+	/*
+	 * We need to request the interrupt here (instead of providing chip
+	 * to the irq directly) because on some platforms several GPIO
+	 * controllers share the same interrupt line.
+	 */
+	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
+			       dev_name(pctrl->dev), pctrl);
+	if (ret) {
+		dev_err(pctrl->dev, "failed to request interrupt\n");
+		goto fail;
 	}
 
 	ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
 				   handle_simple_irq, IRQ_TYPE_NONE);
 	if (ret) {
 		dev_err(pctrl->dev, "failed to add irqchip\n");
-		gpiochip_remove(&pctrl->chip);
-		return ret;
+		goto fail;
 	}
 
 	gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
-				     intel_gpio_irq_handler);
+				     NULL);
 	return 0;
+
+fail:
+	gpiochip_remove(&pctrl->chip);
+
+	return ret;
 }
 
 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
-- 
2.6.1

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#1256731 — Re: [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt

On Wed, Oct 21, 2015 at 12:08 PM, Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:

> On Intel Broxton the GPIO hardware consists of several chips that all share
> the parent interrupt. It is not possible to handle this by setting chained
> handler for each chip (as they will overwrite each other).
>
> To overcome this we need to request the interrupt using devm_request_irq()
> and pass IRQF_SHARED with the flags.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Makes perfect sense. Patch applied.

Yours,
Linus Walleij
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#1256735 — Re: [PATCH 3/3] pinctrl: intel: Add Intel Broxton pin controller support

On Wed, Oct 21, 2015 at 12:08 PM, Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:

> This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO
> controller is based on the same hardware design that is already used in
> Intel Sunrisepoint so we leverage the core driver here.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Excellent work, as usual.
Patch applied for v4.4.

Yours,
Linus Walleij
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