Re: [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt

From	Linus Walleij <linus.walleij@linaro.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt
Date	2015-10-27 13:40 +0100
Message-ID	<qobHI-5cG-13@gated-at.bofh.it> (permalink)
References	<qlYvg-8ai-3@gated-at.bofh.it> <qlYEW-8lO-21@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Wed, Oct 21, 2015 at 12:08 PM, Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:

> On Intel Broxton the GPIO hardware consists of several chips that all share
> the parent interrupt. It is not possible to handle this by setting chained
> handler for each chip (as they will overwrite each other).
>
> To overcome this we need to request the interrupt using devm_request_irq()
> and pass IRQF_SHARED with the flags.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Makes perfect sense. Patch applied.

Yours,
Linus Walleij
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Thread

[PATCH 0/3] pinctrl: Add support for Intel Broxton SoC Mika Westerberg <mika.westerberg@linux.intel.com> - 2015-10-21 12:10 +0200
  [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt Mika Westerberg <mika.westerberg@linux.intel.com> - 2015-10-21 12:20 +0200
    Re: [PATCH 1/3] pinctrl: intel: Add support for multiple GPIO chips  sharing the interrupt Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 13:40 +0100
  Re: [PATCH 3/3] pinctrl: intel: Add Intel Broxton pin controller support Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 13:40 +0100

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