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Groups > comp.lang.forth > #49708
| From | rickman <gnuarm@gmail.com> |
|---|---|
| Newsgroups | comp.lang.forth |
| Subject | Re: Forth in VHDL |
| Date | 2016-07-31 17:10 -0400 |
| Organization | A noiseless patient Spider |
| Message-ID | <nnlpft$qgh$1@dont-email.me> (permalink) |
| References | <nn3ti7$hte$1@dont-email.me> <75a5e2b8-5d09-4f7d-b0b5-0ca36a019752@googlegroups.com> |
On 7/25/2016 8:57 AM, JUERGEN wrote: > On Monday, July 25, 2016 at 3:29:28 AM UTC+1, rickman wrote: >> I wonder how hard it would be to write a Forth in VHDL? It would likely >> be as easy to do in non-synthesizable code as any other language. It >> might be a bit harder in synthesizable code. For one, the I/O would >> need to be constructed from scratch based on some hardware interface. >> The non-synthesizable code could just read from a file... I wonder if >> you can read from the console in VHDL? I've never tried that before. >> >> -- >> >> Rick C > > Forth to Gates - I had a discussion with Ian page last year - he developed C to gates in Oxford if I remember correctly. The product route: Handel-C - then ESL then Celoxica then Mentor. > If you can do C to Gates - Forth to Gates should be easier? > > He stated it should not be too difficult and said: > > "I am willing to give advice, however I’ve been out of academia for 14 years now - and haven’t written a program in any language in all that time! - so I am inevitably going to be rather out of touch with practical aspects which makes me unsure where I might be able to be of real help. The common HDL languages Verilog and VHDL both let you describe functionality which is then converted to gates by the tool (using a process that is not known to me). Another way that is supported in HDLs is instantiation, direct connection of primitives along with higher level blocks. Forth would be ideal for allowing this sort of constructs. If each function is defined in terms of lower level functions down to the primitives available in a given architecture device, it would be a snap to "execute" the top level design which would produce a flat design description or provide for a simulation capability. I guess I am describing a method that is a bit more "ad hoc" than current HDLs. So in some ways it may be a step backwards, but follows in the Forth philosophy of keeping it simple. -- Rick C
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Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:31 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:36 -0700
Re: Forth in VHDL Richard Owlett <rowlett@cloud85.net> - 2016-07-25 08:14 -0500
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 07:37 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 08:01 -0700
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-26 09:43 -0700
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-28 09:12 +0100
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 05:04 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-28 07:56 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 13:04 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-08-02 12:21 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-28 08:02 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-28 15:19 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-31 18:43 -0400
Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-31 17:10 -0700
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-24 20:08 -0700
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-24 20:33 -0700
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:58 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:17 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 10:02 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 14:13 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 14:17 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 15:04 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:28 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 17:20 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 23:07 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-26 03:07 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 13:05 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-26 16:22 -0700
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 03:57 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:34 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 11:15 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 12:51 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 16:12 -0500
Re: Forth in VHDL "Elizabeth D. Rather" <erather@forth.com> - 2016-07-27 12:43 -1000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 00:40 -0400
Re: Forth in VHDL hughaguilar96@gmail.com - 2016-08-02 22:45 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 00:39 -0400
Re: Forth in VHDL wzab01@gmail.com - 2016-07-25 01:48 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:57 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 06:02 -0700
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-30 16:40 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-08-01 08:58 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-31 17:10 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-08-01 09:02 -0700
Re: Forth in VHDL Ilya Tarasov <ilya74.tarasov@gmail.com> - 2016-07-29 05:42 -0700
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