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Re: PCI-enum and SouthBridge behaviour...

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 James Harris wrote:
...
>>> Walking the PCI bus (and other busses connected thereto) should
>>> enumerate everything, shouldn't it, on any PC made in the last 20
>>> years or so? Before that there was PnP which would also allow
>>> enumeration.

>> Yes, but its hard to enumerate a device that dont show up.
>> perhaps thats why windoze need a lot of 'drivers' from mainboard vendor
>> and several reboot cycles to make all these unseen work.

> Microsoft has always had the big advantage that hardware manufacturers 
> will privately tell MS about their devices.

> That said, Linux has to cope with the same problems. Maybe you could look 
> at the Linux source?

C-source ?  it wont show me much I'm afraid :(

I tried to get a clue about hardware features by disassembling a lot of
windoze drivers in the past, but recently I rely only on known hardware
mainly from AMD/ATI, where I'm well supported with documentations.

>>> That said, some chipsets may require special bits to be set in
>>> registers or they will hide some of their hardware. Is that the
>>> problem you are facing?

>> Exact. I suspect that the BIOS modify too many southbridge bits for SATA.
>> I hoped there were known BIOS-functions to overrule this behaviour...

> That does sound like a good use for a BIOS because it would know what 
> idiosyncratic hardware a machine contains. I don't know of any such 
> functions.

RBIL show only the INT1A_B1xx group.

>> Meanwhile I have to run my whole PCI-scan one more time after chip-type
>> recognition and device enabling.

> That may be the only option. I guess that detecting chipset types is not 
> easy to do reliably.

Type detection isn't too hard, just read vendor- and device-ID.
But it would be hard to support all things around today, so I limited
my support to certain known stuff.

> Measures of desperation: I take it there is no way on PCI scanning to 
> reset busses and devices such that the hidden components are revealed?

By any luck SMBUS-config, northbridge and IOs are always visible.

> Any clue in /why/ the BIOS might hide some devices?

Not at all, that's why I posted here.

> Your PCI scan won't take long, will it?

No, only a few mS if I just scan until all desired are found, but a full
scan over all possible 256 busses would take seconds.

__
wolfgang 

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PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-22 21:53 +0200
  Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-24 16:52 +0100
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-24 19:54 +0200
      Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 07:07 +0100
        Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-25 11:04 +0200
          Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 10:30 +0100
            Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-25 14:06 +0200
              Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 13:16 +0100
                Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 13:09 +0200
                Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-26 15:14 +0100
          Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@bcczxcfrze.cam> - 2016-07-25 21:55 -0400
            Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 12:48 +0200
  Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@bcczxcfrze.cam> - 2016-07-26 08:18 -0400
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 20:11 +0200
  Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-28 18:53 +0200
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-29 19:47 +0200
      Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@zxdehrnyya.cam> - 2016-07-29 17:44 -0400
        Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-30 09:44 +0200
    Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-30 12:55 +0100
      Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-30 19:40 +0200
        Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-30 19:08 +0100

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