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Re: PCI-enum and SouthBridge behaviour...

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James Harris replied:

...
>> when I boot from an IDE-connected drive and use BIOS calls like
>> int11/12/14/17 (rather old and useless today anyway) I see much more
>> PCI-devices (EHCI-USB, onboard SOUND and Bridges) than what I see if I
>> boot from an SATA-drive with only a few BIOS calls
>> (int15_e820,int10_0003,int13_4xxx).

>> the BIOS hide or just disable some PCI devices on the type of boot
>> device? or is this any other BIOS function I havent seen so far ?

>> I can of course setup the (known by AMD southbridge docs) PCI-regs to
>> reenable all expected PCI-devices, but why does BIOS disable it ?
>> checked with and without USBtoPS/2 mouse-emulation yet, equal result.  __

> So, when you boot from IDE BIOS tells you one story but when you boot from 
> SATA BIOS tells you a different story about connected devices?

the BIOS disables some USB hosts (regardless of connected things) and
a few other devices too when I boot from SATA drive.

> First thought: Don't use the BIOS if you can avoid it. We know different 
> BIOSes have different bugs. If you can detect what you need by hardware 
> probing then you should be safer.

checked on another machine with different BIOS and a newer AMD-chipset
... same story.

> Walking the PCI bus (and other busses connected thereto) should enumerate 
> everything, shouldn't it, on any PC made in the last 20 years or so? 
> Before that there was PnP which would also allow enumeration.

Yes, but its hard to enumerate a device that dont show up.
perhaps thats why windoze need a lot of 'drivers' from mainboard vendor
and several reboot cycles to make all these unseen work.

> That said, some chipsets may require special bits to be set in registers 
> or they will hide some of their hardware. Is that the problem you are 
> facing?

Exact. I suspect that the BIOS modify too many southbridge bits for SATA.
I hoped there were known BIOS-functions to overrule this behaviour...

Meanwhile I have to run my whole PCI-scan one more time after chip-type
recognition and device enabling.
__
wolfgang 

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Thread

PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-22 21:53 +0200
  Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-24 16:52 +0100
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-24 19:54 +0200
      Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 07:07 +0100
        Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-25 11:04 +0200
          Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 10:30 +0100
            Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-25 14:06 +0200
              Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 13:16 +0100
                Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 13:09 +0200
                Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-26 15:14 +0100
          Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@bcczxcfrze.cam> - 2016-07-25 21:55 -0400
            Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 12:48 +0200
  Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@bcczxcfrze.cam> - 2016-07-26 08:18 -0400
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 20:11 +0200
  Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-28 18:53 +0200
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-29 19:47 +0200
      Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@zxdehrnyya.cam> - 2016-07-29 17:44 -0400
        Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-30 09:44 +0200
    Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-30 12:55 +0100
      Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-30 19:40 +0200
        Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-30 19:08 +0100

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