128/64 division (was: interrupt handling latency and weird register use)

From	anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups	comp.arch
Subject	128/64 division (was: interrupt handling latency and weird register use)
Date	2026-10-28 08:34 +0000
Organization	Institut fuer Computersprachen, Technische Universitaet Wien
Message-ID	<2026Oct28.093427@mips.complang.tuwien.ac.at> (permalink)
References	(3 earlier) <2026Sep1.225146@mips.complang.tuwien.ac.at> <11bpfm8$190ap$1@dont-email.me> <2026Oct27.171414@mips.complang.tuwien.ac.at> <1793120789-5857@newsgrouper.org> <20261027191746.00005584@yahoo.com>

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Michael S <already5chosen@yahoo.com> writes:
>An interesting question here is "Do one has to include 128b / 64b
>division in the ISA or it's better to leave it off?".
>AMD decided that it was needed, but it seems that nobody else followed
>the suit.

The same can be seen already in the 32-bit relatives.  Most (all?)
RISCs just have 32/32 division, if they have division at all, IA-32
has 64/32.  So they continue that in 64-bit RISCs and AMD64.

Given the existing programming languages, the need for 128/64 bit
division is rare (Forth has UM/MOD and SM/REM, which correspond to
AMD64 DIV and IDIV instructions, respectively), and three source
registers does not fit in usual instruction encodings, so most
architectures leave 128/64 to software.

About software implementations: Implementing 128/64 when you only have
64/64 is messy, however.  And general long division is messy in any
case (but I expect that 128/64 helps in that case; certainly n/64 for
arbitrary n is easy with 128/64 and messy with 64/64).

Let's see how expensive they are on a Ryzen 8700G (Zen4, with 128/64
support) and Power8 (without):

Invocations:

# 64/64
time ./gforth-fast -e ': foo #1_000_000_000_000 {: addend :} 1_000_000_000 {: divisor :} addend 100000000 0 do divisor /mod + addend + loop . ; foo bye'
# 128/64
time ./gforth-fast -e ': foo #1_000_000_000_000_000_000_000_000. 1_000_000_000 {: divisor :} divisor 2/ 1- {: dmax :} 100000000 0 do divisor sm/rem swap dmax min loop d. ; foo bye'

64/64  128/64
0.385s 0.424s Ryzen 8700G
1.176s 2.115s Power8

Given the rarity of 128/64, a factor of 2 looks acceptable.  But if
the division was as fast as on Power8 as on the Ryzen 8700G, the
overhead of 128/64 might be a larger factor (that would probably still
be considered acceptable).

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Thread

interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:00 -0300
  Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-01 20:51 +0000
    Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-09-02 12:28 +0000
    Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) makendo <makendo@makendo.invalid> - 2026-10-27 14:17 +0800
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-27 16:14 +0000
        Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 17:06 +0000
          Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Michael S <already5chosen@yahoo.com> - 2026-10-27 19:17 +0200
            Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 20:59 +0000
            128/64 division (was: interrupt handling latency and weird register use) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-28 08:34 +0000
              Re: 128/64 division (was: interrupt handling latency and weird register use) quadibloc@invalid.com (John Savard) - 2026-10-28 11:10 +0000
          Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Terje Mathisen <terje.mathisen@tmsw.no> - 2026-10-27 19:20 +0100
            Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-27 18:49 +0000
            Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) John Levine <johnl@taugh.com> - 2026-10-27 20:08 +0000
              Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) "Brian G. Lucas" <bagel99@gmail.com> - 2026-10-27 17:44 -0400
              Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 12:10 +0000
                Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) John Levine <johnl@taugh.com> - 2026-10-28 16:46 +0000
            Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 12:17 +0000
              Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-28 12:41 +0000
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 19:06 +0000
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-28 16:39 -0500
          Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-27 18:46 +0000
          Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 12:33 +0000
            Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-28 15:20 +0000
            Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-28 15:47 +0000
              Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Josh Vanderhoof <x@y.z> - 2026-10-29 19:25 -0400
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-30 00:30 +0000
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-30 14:01 -0500
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Josh Vanderhoof <x@y.z> - 2026-10-31 01:02 -0400
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Terje Mathisen <terje.mathisen@tmsw.no> - 2026-10-31 08:44 +0100
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-31 15:15 +0000
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Terje Mathisen <terje.mathisen@tmsw.no> - 2026-11-01 09:02 +0100
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Paul Clayton <paaronclayton@gmail.com> - 2026-11-04 23:53 -0500
                Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-31 09:45 +0000
                Re: Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-31 18:27 +0000
                Re: Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-31 19:10 +0000
                Re: Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-11-01 16:11 +0000
                Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V jgd@cix.co.uk (John Dallman) - 2026-10-30 11:50 +0000
            Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-28 15:52 -0500
          Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-29 16:57 +0000
        Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-27 18:45 +0000
        Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-27 13:56 -0500
  Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:43 +0000
  interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Andy Valencia <vandys@vsta.org> - 2026-09-02 08:11 -0700
    Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-09-03 02:59 +0000
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) scott@slp53.sl.home (Scott Lurndal) - 2026-09-03 14:41 +0000
  Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-09-03 02:56 +0000

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