Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
| From | Michael S <already5chosen@yahoo.com> |
|---|---|
| Newsgroups | comp.arch |
| Subject | Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) |
| Date | 2026-10-27 19:17 +0200 |
| Organization | A noiseless patient Spider |
| Message-ID | <20261027191746.00005584@yahoo.com> (permalink) |
| References | (2 earlier) <87ecfcagiw.fsf_-_@debian> <2026Sep1.225146@mips.complang.tuwien.ac.at> <11bpfm8$190ap$1@dont-email.me> <2026Oct27.171414@mips.complang.tuwien.ac.at> <1793120789-5857@newsgrouper.org> |
On Tue, 27 Oct 2026 17:06:29 GMT
MitchAlsup <user5857@newsgrouper.org.invalid> wrote:
>
> Having it perfectly defined is the critical part {bit patterns in,
> bit patterns out} then each implementation can choose for itself
> whether to put it in or leave it out.
>
An interesting question here is "Do one has to include 128b / 64b
division in the ISA or it's better to leave it off?".
AMD decided that it was needed, but it seems that nobody else followed
the suit.
Back to comp.arch | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:00 -0300
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-01 20:51 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-09-02 12:28 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) makendo <makendo@makendo.invalid> - 2026-10-27 14:17 +0800
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-27 16:14 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 17:06 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Michael S <already5chosen@yahoo.com> - 2026-10-27 19:17 +0200
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 20:59 +0000
128/64 division (was: interrupt handling latency and weird register use) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-28 08:34 +0000
Re: 128/64 division (was: interrupt handling latency and weird register use) quadibloc@invalid.com (John Savard) - 2026-10-28 11:10 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Terje Mathisen <terje.mathisen@tmsw.no> - 2026-10-27 19:20 +0100
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-27 18:49 +0000
Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) John Levine <johnl@taugh.com> - 2026-10-27 20:08 +0000
Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) "Brian G. Lucas" <bagel99@gmail.com> - 2026-10-27 17:44 -0400
Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 12:10 +0000
Re: floating point, interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) John Levine <johnl@taugh.com> - 2026-10-28 16:46 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 12:17 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-28 12:41 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 19:06 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-28 16:39 -0500
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-27 18:46 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) antispam@fricas.org (Waldek Hebisch) - 2026-10-28 12:33 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-28 15:20 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-28 15:47 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Josh Vanderhoof <x@y.z> - 2026-10-29 19:25 -0400
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-30 00:30 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-30 14:01 -0500
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Josh Vanderhoof <x@y.z> - 2026-10-31 01:02 -0400
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Terje Mathisen <terje.mathisen@tmsw.no> - 2026-10-31 08:44 +0100
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-31 15:15 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Terje Mathisen <terje.mathisen@tmsw.no> - 2026-11-01 09:02 +0100
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Paul Clayton <paaronclayton@gmail.com> - 2026-11-04 23:53 -0500
Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-31 09:45 +0000
Re: Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-31 18:27 +0000
Re: Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-31 19:10 +0000
Re: Unimplemented opcodes via jump tables (was: interrupt handling latency and weird register use) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-11-01 16:11 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V jgd@cix.co.uk (John Dallman) - 2026-10-30 11:50 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-28 15:52 -0500
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-29 16:57 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) quadibloc@invalid.com (John Savard) - 2026-10-27 18:45 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-10-27 13:56 -0500
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:43 +0000
interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Andy Valencia <vandys@vsta.org> - 2026-09-02 08:11 -0700
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-09-03 02:59 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) scott@slp53.sl.home (Scott Lurndal) - 2026-09-03 14:41 +0000
Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-09-03 02:56 +0000
csiph-web