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Re: Performance of xchg reg,reg

From Michael S <already5chosen@yahoo.com>
Newsgroups comp.arch
Subject Re: Performance of xchg reg,reg
Date 2026-10-14 22:29 +0300
Organization A noiseless patient Spider
Message-ID <20261014222914.0000399e@yahoo.com> (permalink)
References <2026Oct13.104347@mips.complang.tuwien.ac.at>

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On Tue, 13 Oct 2026 08:43:47 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

> Microbenchmarks (and this text in HTML form) on
> <http://www.complang.tuwien.ac.at/anton/xchg/>.
> 
> In compilers, in particular in SSA destruction, or, more generally,
> register allocation, you sometimes have situations where you want to
> swap the contents of registers, e.g., when r1 contains a and r2
> contains b on one path, while r1 contains b and r2 contains a on the
> other path, and both paths join. This can be achieved with 3 mov
> instructions, but requires an extra register. The AMD64 instruction
> set contains the instruction xchg, which swaps the registers without
> extra register.
> 
> More generally, there may be more than two registers whose values have
> to be moved in a cyclic way. This also requires an extra register and
> (for an n-register cycle) n+1 mov instructions if performed using mov
> instructions, or it can be achieved with n-1 xchg instructions.
> 
> Mov instructions are supported very well in recent CPU cores, with the
> cores usually being able to perform as many independent (and often
> even dependent) moves as the register renamer accepts instructions
> (e.g., if the register renamer accepts 8 instructions per cycle, 8
> moves per cycle can be performed, usually even dependent moves).
> 
> But how do xchg instructions perform? Should a register allocator use
> them where they are convenient, or prefer to use mov instructions and
> an extra register?
> 
> <http://www.complang.tuwien.ac.at/anton/xchg/> contains
> microbenchmarks and this posting presents results for them on various
> cores from Intel and AMD.  The first set of microbenchmarks perform 1G
> xchg instructions in a loop containing 28 xchg instructions (plus two
> instructions for the loop).
> 
> One (independent) contains a sequence of 7 xchg instructions that are
> fully independent of each other, all accessing different registers,
> followed by the same sequence another three times. So the xchg
> instructions are as independent as possible with 14 registers
> involved.
> 
> The other (dependent) contains a sequence of 14 xchg instructions
> where each subsequent instruction uses one register of the previous
> instruction, implementing a 15-register cycle. This sequence is
> followed by the reversal of this sequence, resulting in performing the
> 15-register cycle in the other direction.
> 
> Here are the results in Gcycles on recent microarchitectures, i.e., a
> result of 0.25 means that the microarchitecture performs 4 xchg
> instructions per cycle. Smaller is better.
> 
>   indep dep  core        family  CPU 
>   0.26  0.26 Zen5        AMD     Ryzen AI Pro 350
>   0.35  0.35 Zen4        AMD     Ryzen 8700G
>   0.35  0.35 Zen3        AMD     Ryzen 5800X
>   0.61  1.50 Lion Cove   Intel P Core Ultra 225
>   1.00  1.50 Golden Cove Intel P Core i3-1315U
>   0.82  1.50 Rocket Lake Intel P Xeon E-2388G
>   2.07  2.05 Skymont     Intel E Core Ultra 225
>   3.45  3.45 Gracemont   Intel E Core i3-1315U
> 
> Given the results of the dependent benchmark, it looks like the AMD
> processors perform xchg in the register renamer, consuming the
> resources of two ordinary instructions there (probably because two
> result registers are involved).
> 
> On Intel microarchitectures, whether P-cores or E-cores, but
> especially the latter, xchg seems to have gotten little love.
> 
> Let's see how this affects cyclic moves between registers. The
> following microbenchmarks perform cyclic moves through 2-5 registers
> (cyc2-cyc5) in three different ways:
> 
> mem  Store the first register to memory, then perform n-1 moves among
>      registers, then load the memory location into the final register.
> reg  Move the first register into a spare register, then perform n-1
>      moves among the cycled registers, then move the spare register
>      into the final register.
> xchg Use n-1 xchg instructions. 
> 
> The benchmark loop contains 12 cycles, and cycles involving
> non-overlapping sets of registers are benchmarked (6 sets for cyc2, 4
> for cyc3, 3 for cyc4, 2 for cyc5). At least three different memory
> locations are used for holding the value of the first register in
> memory, but the same register is used as the spare register. Here are
> the results (execution cycles per cyclic move (i.e., n+1 movs in case
> of reg, n-1 xchgs in case of xchg).
> 
>     cyc2      |    cyc3      |    cyc4       |    cyc5       |core
> mem  reg  xchg|mem  reg  xchg|mem  reg   xchg|mem  reg   xchg|
> 0.50 0.50 0.27|0.67 0.58 0.52|0.83 0.83  0.77|1.08 0.83  1.02|Zen5
> 1.00 0.51 0.36|1.00 0.68 0.69|1.00 0.85  1.03|1.01 1.01  1.36|Zen4
> 1.00 0.51 0.42|1.00 0.68 0.70|1.00 0.92  1.03|1.02 1.01  1.36|Zen3
> 0.50 0.40 0.68|0.54 0.56 1.28|0.67 0.66  1.97|0.81 0.81  4.21|Lion
> Cove 0.61 0.53 1.00|0.70 0.70 2.00|0.89 0.90  3.00|1.06 1.08
> 4.41|Golden Cove 0.82 0.67 1.00|0.87 0.83 2.00|1.08 1.08  3.00|1.22
> 1.22  4.66|Rocket Lake 1.00 0.40 1.45|0.65 0.73 4.14|0.65 0.65
> 7.35|0.78 0.86  9.44|Skymont 0.67 0.67 3.08|0.83 0.83 6.73|1.03 1.03
> 10.63|1.23 1.23 13.77|Gracemont
> 
> On Zen5, even a 5-register cycle can be profitably implemented with
> xchg when you have no spare register, a 4-register cycle even when you
> have a spare register. For Zen4 and Zen3 cyc4 (for mem) and cyc3 (for
> reg) are borderline cases, and for shorter cycles xchg is better.
> 
> On Intel processors, xchg is so slow that it never is profitable to
> use it. The slowness takes on extreme values in the E-cores, with
> slowdowns by a factor >10 for cyc4 and cyc5.
> 
> - anton


Interesting. Thank you.

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Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-13 08:43 +0000
  Re: Performance of xchg reg,reg Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-14 00:23 +0000
    Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-14 07:00 +0000
      Re: Performance of xchg reg,reg MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-14 22:35 +0000
        Re: Performance of xchg reg,reg Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-14 23:07 +0000
        Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-15 06:05 +0000
          Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-15 07:06 +0000
            Re: Performance of xchg reg,reg EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-16 09:47 -0400
              Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-16 16:04 +0000
              Re: Performance of xchg reg,reg Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-17 05:46 +0000
  Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-14 22:29 +0300
  Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-15 14:21 -0700
    Re: Performance of xchg reg,reg Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-15 21:42 +0000
      Re: Performance of xchg reg,reg Terje Mathisen <terje.mathisen@tmsw.no> - 2026-10-16 14:45 +0200
    Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-16 05:50 +0000
      Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-16 11:34 +0300
        Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-16 18:23 +0000
          Re: Performance of xchg reg,reg scott@slp53.sl.home (Scott Lurndal) - 2026-10-16 20:48 +0000
            Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-16 14:28 -0700
            Re: Performance of xchg reg,reg Thomas Koenig <tkoenig@netcologne.de> - 2026-10-17 09:48 +0000
          Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-17 02:50 +0000
            Re: Performance of xchg reg,reg MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-17 17:11 +0000
              Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-17 17:31 +0000
                Re: Performance of xchg reg,reg MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-17 19:39 +0000
                Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-17 23:20 +0300
                Re: Documentation (was Re: Performance of xchg reg,reg) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-17 20:54 +0000
                Re: Documentation (was Re: Performance of xchg reg,reg) George Neuner <gneuner2@comcast.net> - 2026-10-18 09:45 -0400
                Algol 68 (was: Documentation (was Re: Performance of xchg reg,reg)) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-18 14:08 +0000
                Re: Algol 68 (was: Documentation (was Re: Performance of xchg reg,reg)) quadibloc@invalid.com (John Savard) - 2026-10-19 00:09 +0000
                Re: Algol 68 (was Re: Documentation) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-19 01:46 +0000
                Re: Algol 68 (was Re: Documentation) quadibloc@invalid.com (John Savard) - 2026-10-21 14:15 +0000
                Re: Algol 68 (was Re: Documentation) Niklas Holsti <niklas.holsti@tidorum.invalid> - 2026-10-21 18:34 +0300
                Re: Algol 68 (was Re: Documentation) quadibloc@invalid.com (John Savard) - 2026-10-21 19:38 +0000
                Re: Algol 68 (was Re: Documentation) aph@littlepinkcloud.invalid - 2026-10-22 09:51 +0000
                Re: Algol 68 (was Re: Documentation) Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2026-10-22 14:15 -0700
                Re: Algol 68 (was Re: Documentation) scott@slp53.sl.home (Scott Lurndal) - 2026-10-23 14:08 +0000
                Re: PL/I, was Algol 68 (was: Documentation (was Re: Performance of xchg reg,reg)) John Levine <johnl@taugh.com> - 2026-10-19 03:24 +0000
                Re: PL/I, was Algol 68 (was: Documentation (was Re: Performance of xchg reg,reg)) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-19 05:34 +0000
                Re: Algol 68 Stefan Monnier <monnier@iro.umontreal.ca> - 2026-10-18 23:34 -0400
                Re: Documentation (was Re: Performance of xchg reg,reg) quadibloc@invalid.com (John Savard) - 2026-10-19 00:18 +0000
                Re: Documentation (was Re: Performance of xchg reg,reg) cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-19 01:52 +0000
                Re: Documentation (was Re: Performance of xchg reg,reg) George Neuner <gneuner2@comcast.net> - 2026-10-19 14:50 -0400
                Re: Documentation (was Re: Performance of xchg reg,reg) cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-20 02:05 +0000
                Re: Algol 68 (was Re: Documentation) Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-19 01:54 +0000
                Re: Documentation (was Re: Performance of xchg reg,reg) Thomas Koenig <tkoenig@netcologne.de> - 2026-10-19 07:44 +0000
                Re: Documentation (was Re: Performance of xchg reg,reg) Stefan Monnier <monnier@iro.umontreal.ca> - 2026-10-19 12:24 -0400
                Re: Documentation (was Re: Performance of xchg reg,reg) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-18 17:48 +0000
                Re: Performance of xchg reg,reg George Neuner <gneuner2@comcast.net> - 2026-10-18 08:59 -0400
                Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-18 15:08 +0000
                Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-18 18:43 +0300
                Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-18 16:57 +0000
                Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-18 20:47 +0300
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-18 18:07 +0000
                Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-18 21:04 +0000
                Re: Performance of xchg reg,reg Stefan Monnier <monnier@iro.umontreal.ca> - 2026-10-18 23:43 -0400
                Re: Performance of xchg reg,reg Stephen Fuld <sfuld@alumni.cmu.edu.invalid> - 2026-10-19 06:57 -0700
                Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-19 14:27 -0700
                Re: Performance of xchg reg,reg Stefan Monnier <monnier@iro.umontreal.ca> - 2026-10-20 10:00 -0400
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-20 02:00 +0000
                Re: Performance of xchg reg,reg scott@slp53.sl.home (Scott Lurndal) - 2026-10-20 14:09 +0000
                Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-20 16:44 -0700
                Re: Performance of xchg reg,reg Stefan Monnier <monnier@iro.umontreal.ca> - 2026-10-20 10:05 -0400
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-20 19:56 +0000
                Re: Performance of xchg reg,reg anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-22 10:54 +0000
                Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-22 22:11 +0300
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-18 17:40 +0000
                Re: Performance of xchg reg,reg Michael S <already5chosen@yahoo.com> - 2026-10-18 20:54 +0300
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-18 18:25 +0000
                Re: Performance of xchg reg,reg MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-18 18:01 +0000
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-18 17:59 +0000
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-18 17:09 +0000
                Re: Performance of xchg reg,reg EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-18 12:31 -0400
                Re: Performance of xchg reg,reg cross@spitfire.i.gajendra.net (Dan Cross) - 2026-10-18 17:47 +0000
            Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-18 12:27 -0700
              Re: Performance of xchg reg,reg EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-19 09:38 -0400
                Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-19 14:08 -0700
                Re: Performance of xchg reg,reg Lawrence D’Oliveiro <ldo@nz.invalid> - 2026-10-19 21:21 +0000
                Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-19 14:26 -0700
                Re: Performance of xchg reg,reg Joseph Seigh <jseigh_es00@xemaps.com> - 2026-10-19 19:17 -0400
                Re: Performance of xchg reg,reg "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-19 22:41 -0700
                Re: Performance of xchg reg,reg MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-20 16:45 +0000

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