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Groups > sci.electronics.design > #462497 > unrolled thread
| Started by | klaus.kragelund@gmail.com |
|---|---|
| First post | 2017-05-31 16:08 -0700 |
| Last post | 2017-06-02 12:51 -0400 |
| Articles | 20 on this page of 44 — 9 participants |
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Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-05-31 16:08 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-05-31 19:22 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Klaus Kragelund <klauskvik@hotmail.com> - 2017-05-31 23:27 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 12:58 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Lasse Langwadt Christensen <langwadt@fonz.dk> - 2017-06-01 10:14 -0700
Re: Reliability of microcontroller silicon die glue on top of another die rickman <gnuarm@gmail.com> - 2017-06-01 14:56 -0400
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 18:21 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Lasse Langwadt Christensen <langwadt@fonz.dk> - 2017-06-01 15:37 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 18:40 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Lasse Langwadt Christensen <langwadt@fonz.dk> - 2017-06-01 15:55 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 19:03 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Klaus Kragelund <klauskvik@hotmail.com> - 2017-06-01 16:47 -0700
Re: Reliability of microcontroller silicon die glue on top of another die Klaus Kragelund <klauskvik@hotmail.com> - 2017-06-01 16:51 -0700
Re: Reliability of microcontroller silicon die glue on top of another die pcdhobbs@gmail.com - 2017-06-01 17:09 -0700
Re: Reliability of microcontroller silicon die glue on top of another die Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2017-06-01 17:12 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 20:17 -0400
Re: Reliability of microcontroller silicon die glue on top of another die rickman <gnuarm@gmail.com> - 2017-06-01 20:04 -0400
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 01:13 -0700
Re: Reliability of microcontroller silicon die glue on top of another die rickman <gnuarm@gmail.com> - 2017-06-02 11:21 -0400
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 09:51 -0700
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 10:01 -0700
Re: Reliability of microcontroller silicon die glue on top of another die rickman <gnuarm@gmail.com> - 2017-06-02 13:38 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Klaus Kragelund <klauskvik@hotmail.com> - 2017-06-02 10:47 -0700
Re: Reliability of microcontroller silicon die glue on top of another die rickman <gnuarm@gmail.com> - 2017-06-02 15:22 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Klaus Kragelund <klauskvik@hotmail.com> - 2017-06-02 12:36 -0700
Re: Reliability of microcontroller silicon die glue on top of another die rickman <gnuarm@gmail.com> - 2017-06-02 15:54 -0400
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 20:20 -0400
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-01 20:24 -0400
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 01:19 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-02 12:47 -0400
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 09:56 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-02 17:35 -0400
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 15:43 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-02 18:58 -0400
Re: Reliability of microcontroller silicon die glue on top of another die Klaus Kragelund <klauskvik@hotmail.com> - 2017-06-02 16:27 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-02 19:31 -0400
Re: Reliability of microcontroller silicon die glue on top of another die whit3rd <whit3rd@gmail.com> - 2017-06-03 15:09 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-03 20:35 -0400
Re: Reliability of microcontroller silicon die glue on top of another die whit3rd <whit3rd@gmail.com> - 2017-06-01 20:10 -0700
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 01:22 -0700
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-02 12:50 -0400
Re: Reliability of microcontroller silicon die glue on top of another die klaus.kragelund@gmail.com - 2017-06-02 01:24 -0700
Re: Reliability of microcontroller silicon die glue on top of another die David Brown <david.brown@hesbynett.no> - 2017-06-02 15:38 +0200
Re: Reliability of microcontroller silicon die glue on top of another die krw@notreal.com - 2017-06-02 12:51 -0400
Page 2 of 3 — ← Prev page 1 [2] 3 Next page →
| From | klaus.kragelund@gmail.com |
|---|---|
| Date | 2017-06-02 10:01 -0700 |
| Message-ID | <7f8931fb-e9d5-4a1b-b548-e78530e2ac6a@googlegroups.com> |
| In reply to | #462680 |
On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote: > klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: > > On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: > >> Klaus Kragelund wrote on 6/1/2017 7:47 PM: > >>> Datasheet: > >>> > >>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> > >> WTF? You had to find the data sheet on a third party web site??? > >> > >> Ok, I dug a bit at gsense.com and it seems they are the parent company. How > >> did you find the data sheet? > >> > > > > Google is your friend > > If I have to use Google to find a data sheet, I figure the company must not > make the parts anymore or at least aren't looking for sales. > > > >>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >> > >> Where did you get a price? > >> > > > > Page 11: > > > > http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf > > Ok, a BS marketing price. Which part, what quantity... > > > >>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >> > >> Huh? Having two die is not so cheap. If two separate die are "always" > >> better, why do they combine the Flash with CPU in most cases for chips in > >> this range? > >> > > > > In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology > > Who says it is cheaper? If you can't buy them it doesn't matter. I can't > find anyone who sells them. > > > >>> Operation from SRAM draws less current > >> > >> I don't see that in the numbers in the data sheet. ~300 uA/MHz. > >> > > > > It's not specifically stated. For reference look up the STM32 datasheet > > The point is 300 uA/MHz is not even in the running for low power these days. > The fact that running from SRAM *should* use less current doesn't mean > their chips are competitive. I believe the forefront of low power ARMs is > in the 100 uA/MHz these days. Am I mistaken? > > -- Check for example the STM32F130 datasheet, page 42: http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf SRAM is about 10% lower power consumption than flash Cheers Klaus
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| From | rickman <gnuarm@gmail.com> |
|---|---|
| Date | 2017-06-02 13:38 -0400 |
| Message-ID | <ogs7kf$6qi$1@dont-email.me> |
| In reply to | #462701 |
klaus.kragelund@gmail.com wrote on 6/2/2017 1:01 PM: > On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote: >> klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: >>> On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: >>>> Klaus Kragelund wrote on 6/1/2017 7:47 PM: >>>>> Datasheet: >>>>> >>>>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >>>> >>>> WTF? You had to find the data sheet on a third party web site??? >>>> >>>> Ok, I dug a bit at gsense.com and it seems they are the parent company. How >>>> did you find the data sheet? >>>> >>> >>> Google is your friend >> >> If I have to use Google to find a data sheet, I figure the company must not >> make the parts anymore or at least aren't looking for sales. >> >> >>>>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >>>> >>>> Where did you get a price? >>>> >>> >>> Page 11: >>> >>> http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf >> >> Ok, a BS marketing price. Which part, what quantity... >> >> >>>>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >>>> >>>> Huh? Having two die is not so cheap. If two separate die are "always" >>>> better, why do they combine the Flash with CPU in most cases for chips in >>>> this range? >>>> >>> >>> In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology >> >> Who says it is cheaper? If you can't buy them it doesn't matter. I can't >> find anyone who sells them. >> >> >>>>> Operation from SRAM draws less current >>>> >>>> I don't see that in the numbers in the data sheet. ~300 uA/MHz. >>>> >>> >>> It's not specifically stated. For reference look up the STM32 datasheet >> >> The point is 300 uA/MHz is not even in the running for low power these days. >> The fact that running from SRAM *should* use less current doesn't mean >> their chips are competitive. I believe the forefront of low power ARMs is >> in the 100 uA/MHz these days. Am I mistaken? >> >> -- > Check for example the STM32F130 datasheet, page 42: > > http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf > > SRAM is about 10% lower power consumption than flash You are comparing the Giga part to an ST part that is 10 years old, right? 300 uA/MHz is not on the forefront of power efficiency. TI and Silicon Labs have CM3 and CM4 parts that can reach power consumption below 100 uA/MHz. The issue is not about features but about specifications. I don't care how an MCU gets low power. The Giga part is not in the realm of what is considered low power anymore. -- Rick C
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| From | Klaus Kragelund <klauskvik@hotmail.com> |
|---|---|
| Date | 2017-06-02 10:47 -0700 |
| Message-ID | <e961b4b6-5225-4ea3-9685-5688db09cdaf@googlegroups.com> |
| In reply to | #462709 |
On Friday, June 2, 2017 at 7:38:46 PM UTC+2, rickman wrote: > klaus.kragelund@gmail.com wrote on 6/2/2017 1:01 PM: > > On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote: > >> klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: > >>> On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: > >>>> Klaus Kragelund wrote on 6/1/2017 7:47 PM: > >>>>> Datasheet: > >>>>> > >>>>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >>>> > >>>> WTF? You had to find the data sheet on a third party web site??? > >>>> > >>>> Ok, I dug a bit at gsense.com and it seems they are the parent company. How > >>>> did you find the data sheet? > >>>> > >>> > >>> Google is your friend > >> > >> If I have to use Google to find a data sheet, I figure the company must not > >> make the parts anymore or at least aren't looking for sales. > >> > >> > >>>>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >>>> > >>>> Where did you get a price? > >>>> > >>> > >>> Page 11: > >>> > >>> http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf > >> > >> Ok, a BS marketing price. Which part, what quantity... > >> > >> > >>>>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >>>> > >>>> Huh? Having two die is not so cheap. If two separate die are "always" > >>>> better, why do they combine the Flash with CPU in most cases for chips in > >>>> this range? > >>>> > >>> > >>> In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology > >> > >> Who says it is cheaper? If you can't buy them it doesn't matter. I can't > >> find anyone who sells them. > >> > >> > >>>>> Operation from SRAM draws less current > >>>> > >>>> I don't see that in the numbers in the data sheet. ~300 uA/MHz. > >>>> > >>> > >>> It's not specifically stated. For reference look up the STM32 datasheet > >> > >> The point is 300 uA/MHz is not even in the running for low power these days. > >> The fact that running from SRAM *should* use less current doesn't mean > >> their chips are competitive. I believe the forefront of low power ARMs is > >> in the 100 uA/MHz these days. Am I mistaken? > >> > >> -- > > Check for example the STM32F130 datasheet, page 42: > > > > http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf > > > > SRAM is about 10% lower power consumption than flash > > You are comparing the Giga part to an ST part that is 10 years old, right? > 300 uA/MHz is not on the forefront of power efficiency. TI and Silicon Labs > have CM3 and CM4 parts that can reach power consumption below 100 uA/MHz. > > The issue is not about features but about specifications. I don't care how > an MCU gets low power. The Giga part is not in the realm of what is > considered low power anymore. > Yes, but you certainly won't get a low power ST part in that price range Low power is a sales feature until they all have that feature 😀 Comparing apples to apples 🍎 Cheers Klaus
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| From | rickman <gnuarm@gmail.com> |
|---|---|
| Date | 2017-06-02 15:22 -0400 |
| Message-ID | <ogsdnf$85q$1@dont-email.me> |
| In reply to | #462713 |
Klaus Kragelund wrote on 6/2/2017 1:47 PM: > On Friday, June 2, 2017 at 7:38:46 PM UTC+2, rickman wrote: >> klaus.kragelund@gmail.com wrote on 6/2/2017 1:01 PM: >>> On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote: >>>> klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: >>>>> On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: >>>>>> Klaus Kragelund wrote on 6/1/2017 7:47 PM: >>>>>>> Datasheet: >>>>>>> >>>>>>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >>>>>> >>>>>> WTF? You had to find the data sheet on a third party web site??? >>>>>> >>>>>> Ok, I dug a bit at gsense.com and it seems they are the parent company. How >>>>>> did you find the data sheet? >>>>>> >>>>> >>>>> Google is your friend >>>> >>>> If I have to use Google to find a data sheet, I figure the company must not >>>> make the parts anymore or at least aren't looking for sales. >>>> >>>> >>>>>>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >>>>>> >>>>>> Where did you get a price? >>>>>> >>>>> >>>>> Page 11: >>>>> >>>>> http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf >>>> >>>> Ok, a BS marketing price. Which part, what quantity... >>>> >>>> >>>>>>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >>>>>> >>>>>> Huh? Having two die is not so cheap. If two separate die are "always" >>>>>> better, why do they combine the Flash with CPU in most cases for chips in >>>>>> this range? >>>>>> >>>>> >>>>> In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology >>>> >>>> Who says it is cheaper? If you can't buy them it doesn't matter. I can't >>>> find anyone who sells them. >>>> >>>> >>>>>>> Operation from SRAM draws less current >>>>>> >>>>>> I don't see that in the numbers in the data sheet. ~300 uA/MHz. >>>>>> >>>>> >>>>> It's not specifically stated. For reference look up the STM32 datasheet >>>> >>>> The point is 300 uA/MHz is not even in the running for low power these days. >>>> The fact that running from SRAM *should* use less current doesn't mean >>>> their chips are competitive. I believe the forefront of low power ARMs is >>>> in the 100 uA/MHz these days. Am I mistaken? >>>> >>>> -- >>> Check for example the STM32F130 datasheet, page 42: >>> >>> http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf >>> >>> SRAM is about 10% lower power consumption than flash >> >> You are comparing the Giga part to an ST part that is 10 years old, right? >> 300 uA/MHz is not on the forefront of power efficiency. TI and Silicon Labs >> have CM3 and CM4 parts that can reach power consumption below 100 uA/MHz. >> >> The issue is not about features but about specifications. I don't care how >> an MCU gets low power. The Giga part is not in the realm of what is >> considered low power anymore. >> > Yes, but you certainly won't get a low power ST part in that price range > > Low power is a sales feature until they all have that feature 😀 > > Comparing apples to apples 🍎 The point is you are claiming the use of an external Flash allows *lower* power operation. That is irrelevant when the chip spec is *much* worse than others in the same performance class. If you want to compare prices, then compare prices. This isn't about apples. The $0.30 price is not a quote, it is a mythical price based on buying some enormous quantity. Since their parts aren't actually offered for sale anywhere that I would be buying them it doesn't matter what price a marketing sheet says they go for. I did find Symmetry that offers them for $0.71. -- Rick C
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| From | Klaus Kragelund <klauskvik@hotmail.com> |
|---|---|
| Date | 2017-06-02 12:36 -0700 |
| Message-ID | <581c107f-c5ac-451a-8f94-ee91470b05ff@googlegroups.com> |
| In reply to | #462736 |
On Friday, June 2, 2017 at 9:22:46 PM UTC+2, rickman wrote: > Klaus Kragelund wrote on 6/2/2017 1:47 PM: > > On Friday, June 2, 2017 at 7:38:46 PM UTC+2, rickman wrote: > >> klaus.kragelund@gmail.com wrote on 6/2/2017 1:01 PM: > >>> On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote: > >>>> klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: > >>>>> On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: > >>>>>> Klaus Kragelund wrote on 6/1/2017 7:47 PM: > >>>>>>> Datasheet: > >>>>>>> > >>>>>>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >>>>>> > >>>>>> WTF? You had to find the data sheet on a third party web site??? > >>>>>> > >>>>>> Ok, I dug a bit at gsense.com and it seems they are the parent company. How > >>>>>> did you find the data sheet? > >>>>>> > >>>>> > >>>>> Google is your friend > >>>> > >>>> If I have to use Google to find a data sheet, I figure the company must not > >>>> make the parts anymore or at least aren't looking for sales. > >>>> > >>>> > >>>>>>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >>>>>> > >>>>>> Where did you get a price? > >>>>>> > >>>>> > >>>>> Page 11: > >>>>> > >>>>> http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf > >>>> > >>>> Ok, a BS marketing price. Which part, what quantity... > >>>> > >>>> > >>>>>>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >>>>>> > >>>>>> Huh? Having two die is not so cheap. If two separate die are "always" > >>>>>> better, why do they combine the Flash with CPU in most cases for chips in > >>>>>> this range? > >>>>>> > >>>>> > >>>>> In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology > >>>> > >>>> Who says it is cheaper? If you can't buy them it doesn't matter. I can't > >>>> find anyone who sells them. > >>>> > >>>> > >>>>>>> Operation from SRAM draws less current > >>>>>> > >>>>>> I don't see that in the numbers in the data sheet. ~300 uA/MHz. > >>>>>> > >>>>> > >>>>> It's not specifically stated. For reference look up the STM32 datasheet > >>>> > >>>> The point is 300 uA/MHz is not even in the running for low power these days. > >>>> The fact that running from SRAM *should* use less current doesn't mean > >>>> their chips are competitive. I believe the forefront of low power ARMs is > >>>> in the 100 uA/MHz these days. Am I mistaken? > >>>> > >>>> -- > >>> Check for example the STM32F130 datasheet, page 42: > >>> > >>> http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf > >>> > >>> SRAM is about 10% lower power consumption than flash > >> > >> You are comparing the Giga part to an ST part that is 10 years old, right? > >> 300 uA/MHz is not on the forefront of power efficiency. TI and Silicon Labs > >> have CM3 and CM4 parts that can reach power consumption below 100 uA/MHz. > >> > >> The issue is not about features but about specifications. I don't care how > >> an MCU gets low power. The Giga part is not in the realm of what is > >> considered low power anymore. > >> > > Yes, but you certainly won't get a low power ST part in that price range > > > > Low power is a sales feature until they all have that feature 😀 > > > > Comparing apples to apples 🍎 > > The point is you are claiming the use of an external Flash allows *lower* > power operation. That is irrelevant when the chip spec is *much* worse than > others in the same performance class. If you want to compare prices, then > compare prices. This isn't about apples. > > The $0.30 price is not a quote, it is a mythical price based on buying some > enormous quantity. Since their parts aren't actually offered for sale > anywhere that I would be buying them it doesn't matter what price a > marketing sheet says they go for. I did find Symmetry that offers them for > $0.71. > Some parts are not offered in public, they are offered with distributors frame work agreements Cheers Klaus
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| From | rickman <gnuarm@gmail.com> |
|---|---|
| Date | 2017-06-02 15:54 -0400 |
| Message-ID | <ogsfih$eb2$1@dont-email.me> |
| In reply to | #462738 |
Klaus Kragelund wrote on 6/2/2017 3:36 PM: > On Friday, June 2, 2017 at 9:22:46 PM UTC+2, rickman wrote: >> Klaus Kragelund wrote on 6/2/2017 1:47 PM: >>> On Friday, June 2, 2017 at 7:38:46 PM UTC+2, rickman wrote: >>>> klaus.kragelund@gmail.com wrote on 6/2/2017 1:01 PM: >>>>> On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote: >>>>>> klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: >>>>>>> On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: >>>>>>>> Klaus Kragelund wrote on 6/1/2017 7:47 PM: >>>>>>>>> Datasheet: >>>>>>>>> >>>>>>>>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >>>>>>>> >>>>>>>> WTF? You had to find the data sheet on a third party web site??? >>>>>>>> >>>>>>>> Ok, I dug a bit at gsense.com and it seems they are the parent company. How >>>>>>>> did you find the data sheet? >>>>>>>> >>>>>>> >>>>>>> Google is your friend >>>>>> >>>>>> If I have to use Google to find a data sheet, I figure the company must not >>>>>> make the parts anymore or at least aren't looking for sales. >>>>>> >>>>>> >>>>>>>>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >>>>>>>> >>>>>>>> Where did you get a price? >>>>>>>> >>>>>>> >>>>>>> Page 11: >>>>>>> >>>>>>> http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf >>>>>> >>>>>> Ok, a BS marketing price. Which part, what quantity... >>>>>> >>>>>> >>>>>>>>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >>>>>>>> >>>>>>>> Huh? Having two die is not so cheap. If two separate die are "always" >>>>>>>> better, why do they combine the Flash with CPU in most cases for chips in >>>>>>>> this range? >>>>>>>> >>>>>>> >>>>>>> In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology >>>>>> >>>>>> Who says it is cheaper? If you can't buy them it doesn't matter. I can't >>>>>> find anyone who sells them. >>>>>> >>>>>> >>>>>>>>> Operation from SRAM draws less current >>>>>>>> >>>>>>>> I don't see that in the numbers in the data sheet. ~300 uA/MHz. >>>>>>>> >>>>>>> >>>>>>> It's not specifically stated. For reference look up the STM32 datasheet >>>>>> >>>>>> The point is 300 uA/MHz is not even in the running for low power these days. >>>>>> The fact that running from SRAM *should* use less current doesn't mean >>>>>> their chips are competitive. I believe the forefront of low power ARMs is >>>>>> in the 100 uA/MHz these days. Am I mistaken? >>>>>> >>>>>> -- >>>>> Check for example the STM32F130 datasheet, page 42: >>>>> >>>>> http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf >>>>> >>>>> SRAM is about 10% lower power consumption than flash >>>> >>>> You are comparing the Giga part to an ST part that is 10 years old, right? >>>> 300 uA/MHz is not on the forefront of power efficiency. TI and Silicon Labs >>>> have CM3 and CM4 parts that can reach power consumption below 100 uA/MHz. >>>> >>>> The issue is not about features but about specifications. I don't care how >>>> an MCU gets low power. The Giga part is not in the realm of what is >>>> considered low power anymore. >>>> >>> Yes, but you certainly won't get a low power ST part in that price range >>> >>> Low power is a sales feature until they all have that feature 😀 >>> >>> Comparing apples to apples 🍎 >> >> The point is you are claiming the use of an external Flash allows *lower* >> power operation. That is irrelevant when the chip spec is *much* worse than >> others in the same performance class. If you want to compare prices, then >> compare prices. This isn't about apples. >> >> The $0.30 price is not a quote, it is a mythical price based on buying some >> enormous quantity. Since their parts aren't actually offered for sale >> anywhere that I would be buying them it doesn't matter what price a >> marketing sheet says they go for. I did find Symmetry that offers them for >> $0.71. >> > Some parts are not offered in public, they are offered with distributors frame work agreements In other words, if you aren't buying a million a year, buzz off! Got it! -- Rick C
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-01 20:20 -0400 |
| Message-ID | <lnb1jct5aehn43r00v3bjv4ml5dh749194@4ax.com> |
| In reply to | #462631 |
On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund <klauskvik@hotmail.com> wrote: >Datasheet: > >http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >Price = 0.3 USD in volume, at least 25% cheaper than the STM32 Where? > >The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies That's certainly not true. If it were, there wouldn't be mixed technology chips. >Operation from SRAM draws less current Not buying it, at least reads (operation). Note that both are zero wait-states so no advantage there.
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-01 20:24 -0400 |
| Message-ID | <7vb1jc96dn3e2chs41jgnhvk86sa7od36a@4ax.com> |
| In reply to | #462637 |
On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund ><klauskvik@hotmail.com> wrote: > >>Datasheet: >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >Where? >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >That's certainly not true. If it were, there wouldn't be mixed >technology chips. > >>Operation from SRAM draws less current > >Not buying it, at least reads (operation). Note that both are zero >wait-states so no advantage there. BTW, the datasheet claims 3MB "on-chip" flash? That's not what we were discussing (and *really* hard to believe). I shoulda checked the date on the datasheet (4/1? ;).
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| From | klaus.kragelund@gmail.com |
|---|---|
| Date | 2017-06-02 01:19 -0700 |
| Message-ID | <acf0957a-76f2-4b47-a6ac-dcc7abc6139f@googlegroups.com> |
| In reply to | #462638 |
On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: > On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: > > >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund > ><klauskvik@hotmail.com> wrote: > > > >>Datasheet: > >> > >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> > >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > > > >Where? > >> > >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > > > >That's certainly not true. If it were, there wouldn't be mixed > >technology chips. > > > >>Operation from SRAM draws less current > > > >Not buying it, at least reads (operation). Note that both are zero > >wait-states so no advantage there. > > BTW, the datasheet claims 3MB "on-chip" flash? That's not what we > were discussing (and *really* hard to believe). I shoulda checked the > date on the datasheet (4/1? ;). Check the reverse engineering document. They have serial flash, so it is up to 3MB Cheers Klaus
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-02 12:47 -0400 |
| Message-ID | <kh53jc1ea6c7er1752g9g1g89h9j8ra175@4ax.com> |
| In reply to | #462659 |
On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com wrote: >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund >> ><klauskvik@hotmail.com> wrote: >> > >> >>Datasheet: >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> > >> >Where? >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> > >> >That's certainly not true. If it were, there wouldn't be mixed >> >technology chips. >> > >> >>Operation from SRAM draws less current >> > >> >Not buying it, at least reads (operation). Note that both are zero >> >wait-states so no advantage there. >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we >> were discussing (and *really* hard to believe). I shoulda checked the >> date on the datasheet (4/1? ;). > >Check the reverse engineering document. They have serial flash, so it is up to 3MB You've said so many things contrary to the datasheet and yourself, and it's equally opaque, that I have no idea what you're talking about anymore.
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| From | klaus.kragelund@gmail.com |
|---|---|
| Date | 2017-06-02 09:56 -0700 |
| Message-ID | <375a0105-b8e8-4e36-a1e6-06cb72fd0c97@googlegroups.com> |
| In reply to | #462691 |
On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: > On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com > wrote: > > >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: > >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: > >> > >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund > >> ><klauskvik@hotmail.com> wrote: > >> > > >> >>Datasheet: > >> >> > >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> >> > >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >> > > >> >Where? > >> >> > >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >> > > >> >That's certainly not true. If it were, there wouldn't be mixed > >> >technology chips. > >> > > >> >>Operation from SRAM draws less current > >> > > >> >Not buying it, at least reads (operation). Note that both are zero > >> >wait-states so no advantage there. > >> > >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we > >> were discussing (and *really* hard to believe). I shoulda checked the > >> date on the datasheet (4/1? ;). > > > >Check the reverse engineering document. They have serial flash, so it is up to 3MB > > You've said so many things contrary to the datasheet and yourself, and > it's equally opaque, that I have no idea what you're talking about > anymore. Name them, I do not think I have stated anything misleading?
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-02 17:35 -0400 |
| Message-ID | <cem3jc5bemr7lcu35jtf8rnjt4t8b1ad7k@4ax.com> |
| In reply to | #462697 |
On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com wrote: >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com >> wrote: >> >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >> >> >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund >> >> ><klauskvik@hotmail.com> wrote: >> >> > >> >> >>Datasheet: >> >> >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> >> > >> >> >Where? >> >> >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> >> > >> >> >That's certainly not true. If it were, there wouldn't be mixed >> >> >technology chips. >> >> > >> >> >>Operation from SRAM draws less current >> >> > >> >> >Not buying it, at least reads (operation). Note that both are zero >> >> >wait-states so no advantage there. >> >> >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we >> >> were discussing (and *really* hard to believe). I shoulda checked the >> >> date on the datasheet (4/1? ;). >> > >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB >> >> You've said so many things contrary to the datasheet and yourself, and >> it's equally opaque, that I have no idea what you're talking about >> anymore. > >Name them, I do not think I have stated anything misleading? Is the flash on-chip or not? Is the power lower operating from flash, or not? (Hint: if it's a flash part, it's not operating, with zero wait-state, from flash). Are you really the distributor for this junk?
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| From | klaus.kragelund@gmail.com |
|---|---|
| Date | 2017-06-02 15:43 -0700 |
| Message-ID | <cc677ad9-3914-47d2-a19a-a633994fc342@googlegroups.com> |
| In reply to | #462751 |
On Friday, 2 June 2017 23:35:33 UTC+2, k...@notreal.com wrote: > On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com > wrote: > > >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: > >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com > >> wrote: > >> > >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: > >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: > >> >> > >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund > >> >> ><klauskvik@hotmail.com> wrote: > >> >> > > >> >> >>Datasheet: > >> >> >> > >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> >> >> > >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >> >> > > >> >> >Where? > >> >> >> > >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >> >> > > >> >> >That's certainly not true. If it were, there wouldn't be mixed > >> >> >technology chips. > >> >> > > >> >> >>Operation from SRAM draws less current > >> >> > > >> >> >Not buying it, at least reads (operation). Note that both are zero > >> >> >wait-states so no advantage there. > >> >> > >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we > >> >> were discussing (and *really* hard to believe). I shoulda checked the > >> >> date on the datasheet (4/1? ;). > >> > > >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB > >> > >> You've said so many things contrary to the datasheet and yourself, and > >> it's equally opaque, that I have no idea what you're talking about > >> anymore. > > > >Name them, I do not think I have stated anything misleading? > > Is the flash on-chip or not? That was shown in the original post, this link: https://www.google.com/url?q=https%3A%2F%2Fzeptobars.com%2Fen%2Fread%2FGD32F103CBT6-mcm-serial-flash-Giga-Devices&sa=D&sntz=1&usg=AFQjCNGxP01l8TwSoAUL0fUySa4gGXhUYw 2 dies. AFAICT the flash is loaded to SRAM during startup (50ms startup), and then excutions runs in SRAM, hence the 0 wait state >Is the power lower operating from flash, > or not? (Hint: if it's a flash part, it's not operating, with zero > wait-state, from flash). Lower from SRAM, datasheet does not state the figure explicitly > > Are you really the distributor for this junk? Yes, sure, been lurking in this NG for 20 years, for the hope that you would come by and pressure me for free samples. Cheers Klaus
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-02 18:58 -0400 |
| Message-ID | <67r3jc5gbpujnkn0hap1mp0q9nc1ses3mf@4ax.com> |
| In reply to | #462757 |
On Fri, 2 Jun 2017 15:43:27 -0700 (PDT), klaus.kragelund@gmail.com wrote: >On Friday, 2 June 2017 23:35:33 UTC+2, k...@notreal.com wrote: >> On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com >> wrote: >> >> >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: >> >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com >> >> wrote: >> >> >> >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: >> >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >> >> >> >> >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund >> >> >> ><klauskvik@hotmail.com> wrote: >> >> >> > >> >> >> >>Datasheet: >> >> >> >> >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> >> >> >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> >> >> > >> >> >> >Where? >> >> >> >> >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> >> >> > >> >> >> >That's certainly not true. If it were, there wouldn't be mixed >> >> >> >technology chips. >> >> >> > >> >> >> >>Operation from SRAM draws less current >> >> >> > >> >> >> >Not buying it, at least reads (operation). Note that both are zero >> >> >> >wait-states so no advantage there. >> >> >> >> >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we >> >> >> were discussing (and *really* hard to believe). I shoulda checked the >> >> >> date on the datasheet (4/1? ;). >> >> > >> >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB >> >> >> >> You've said so many things contrary to the datasheet and yourself, and >> >> it's equally opaque, that I have no idea what you're talking about >> >> anymore. >> > >> >Name them, I do not think I have stated anything misleading? >> >> Is the flash on-chip or not? > >That was shown in the original post, this link: > >https://www.google.com/url?q=https%3A%2F%2Fzeptobars.com%2Fen%2Fread%2FGD32F103CBT6-mcm-serial-flash-Giga-Devices&sa=D&sntz=1&usg=AFQjCNGxP01l8TwSoAUL0fUySa4gGXhUYw > >2 dies. AFAICT the flash is loaded to SRAM during startup (50ms startup), and then excutions runs in SRAM, hence the 0 wait state The datasheet (and you) claimed that it was a single chip. You also claimed that it was faster when operating out of SRAM than flash. Obviously false, since it can't operate out of flash. >>Is the power lower operating from flash, >> or not? (Hint: if it's a flash part, it's not operating, with zero >> wait-state, from flash). > >Lower from SRAM, datasheet does not state the figure explicitly But it *can't*. <sheesh!> >> >> Are you really the distributor for this junk? > >Yes, sure, been lurking in this NG for 20 years, for the hope that you would come by and pressure me for free samples. I don't waste time on junk but you're welcome to drool over it some more.
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| From | Klaus Kragelund <klauskvik@hotmail.com> |
|---|---|
| Date | 2017-06-02 16:27 -0700 |
| Message-ID | <f1afffbf-cfc8-45ff-a4a9-b605c66a8119@googlegroups.com> |
| In reply to | #462765 |
On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote: > On Fri, 2 Jun 2017 15:43:27 -0700 (PDT), klaus.kragelund@gmail.com > wrote: > > >On Friday, 2 June 2017 23:35:33 UTC+2, k...@notreal.com wrote: > >> On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com > >> wrote: > >> > >> >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: > >> >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com > >> >> wrote: > >> >> > >> >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: > >> >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: > >> >> >> > >> >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund > >> >> >> ><klauskvik@hotmail.com> wrote: > >> >> >> > > >> >> >> >>Datasheet: > >> >> >> >> > >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> >> >> >> > >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >> >> >> > > >> >> >> >Where? > >> >> >> >> > >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >> >> >> > > >> >> >> >That's certainly not true. If it were, there wouldn't be mixed > >> >> >> >technology chips. > >> >> >> > > >> >> >> >>Operation from SRAM draws less current > >> >> >> > > >> >> >> >Not buying it, at least reads (operation). Note that both are zero > >> >> >> >wait-states so no advantage there. > >> >> >> > >> >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we > >> >> >> were discussing (and *really* hard to believe). I shoulda checked the > >> >> >> date on the datasheet (4/1? ;). > >> >> > > >> >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB > >> >> > >> >> You've said so many things contrary to the datasheet and yourself, and > >> >> it's equally opaque, that I have no idea what you're talking about > >> >> anymore. > >> > > >> >Name them, I do not think I have stated anything misleading? > >> > >> Is the flash on-chip or not? > > > >That was shown in the original post, this link: > > > >https://www.google.com/url?q=https%3A%2F%2Fzeptobars.com%2Fen%2Fread%2FGD32F103CBT6-mcm-serial-flash-Giga-Devices&sa=D&sntz=1&usg=AFQjCNGxP01l8TwSoAUL0fUySa4gGXhUYw > > > >2 dies. AFAICT the flash is loaded to SRAM during startup (50ms startup), and then excutions runs in SRAM, hence the 0 wait state > > The datasheet (and you) claimed that it was a single chip. [snip] NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution...
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-02 19:31 -0400 |
| Message-ID | <5at3jc5l61abfdg4sn1gb7e30f4i3mlilk@4ax.com> |
| In reply to | #462772 |
On Fri, 2 Jun 2017 16:27:01 -0700 (PDT), Klaus Kragelund <klauskvik@hotmail.com> wrote: >On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote: >> On Fri, 2 Jun 2017 15:43:27 -0700 (PDT), klaus.kragelund@gmail.com >> wrote: >> >> >On Friday, 2 June 2017 23:35:33 UTC+2, k...@notreal.com wrote: >> >> On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com >> >> wrote: >> >> >> >> >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: >> >> >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com >> >> >> wrote: >> >> >> >> >> >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: >> >> >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >> >> >> >> >> >> >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund >> >> >> >> ><klauskvik@hotmail.com> wrote: >> >> >> >> > >> >> >> >> >>Datasheet: >> >> >> >> >> >> >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> >> >> >> >> >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> >> >> >> > >> >> >> >> >Where? >> >> >> >> >> >> >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> >> >> >> > >> >> >> >> >That's certainly not true. If it were, there wouldn't be mixed >> >> >> >> >technology chips. >> >> >> >> > >> >> >> >> >>Operation from SRAM draws less current >> >> >> >> > >> >> >> >> >Not buying it, at least reads (operation). Note that both are zero >> >> >> >> >wait-states so no advantage there. >> >> >> >> >> >> >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we >> >> >> >> were discussing (and *really* hard to believe). I shoulda checked the >> >> >> >> date on the datasheet (4/1? ;). >> >> >> > >> >> >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB >> >> >> >> >> >> You've said so many things contrary to the datasheet and yourself, and >> >> >> it's equally opaque, that I have no idea what you're talking about >> >> >> anymore. >> >> > >> >> >Name them, I do not think I have stated anything misleading? >> >> >> >> Is the flash on-chip or not? >> > >> >That was shown in the original post, this link: >> > >> >https://www.google.com/url?q=https%3A%2F%2Fzeptobars.com%2Fen%2Fread%2FGD32F103CBT6-mcm-serial-flash-Giga-Devices&sa=D&sntz=1&usg=AFQjCNGxP01l8TwSoAUL0fUySa4gGXhUYw >> > >> >2 dies. AFAICT the flash is loaded to SRAM during startup (50ms startup), and then excutions runs in SRAM, hence the 0 wait state >> >> The datasheet (and you) claimed that it was a single chip. > >[snip] > >NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution... But then you kept saying "on chip", as does the datasheet. It's not. It's a kludge.
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| From | whit3rd <whit3rd@gmail.com> |
|---|---|
| Date | 2017-06-03 15:09 -0700 |
| Message-ID | <800088f7-fcfc-4592-a170-ab1a8f4f64d6@googlegroups.com> |
| In reply to | #462774 |
On Friday, June 2, 2017 at 4:31:59 PM UTC-7, k...@notreal.com wrote: > On Fri, 2 Jun 2017 16:27:01 -0700 (PDT), Klaus Kragelund > <klauskvik@hotmail.com> wrote: > > >On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote: > >> The datasheet (and you) claimed that it was a single chip. > >NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution... > > But then you kept saying "on chip", as does the datasheet. It's not. > It's a kludge. One chip, with two dice. The flash is useful as a read-mainly store, so the odd mounting makes some sense. It doesn't NEED heatsinking, or lots of wire connection. I'm uncertain what "it's a kludge" signifies. Does this relate to your filing system "put this in the folder marked KLUDGE"? Folders marked "miscellaneous' don't make sense either.
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| From | krw@notreal.com |
|---|---|
| Date | 2017-06-03 20:35 -0400 |
| Message-ID | <lcl6jcle5upkucnqm61950rig3e6edcqgc@4ax.com> |
| In reply to | #462891 |
On Sat, 3 Jun 2017 15:09:41 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote: >On Friday, June 2, 2017 at 4:31:59 PM UTC-7, k...@notreal.com wrote: >> On Fri, 2 Jun 2017 16:27:01 -0700 (PDT), Klaus Kragelund >> <klauskvik@hotmail.com> wrote: >> >> >On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote: > >> >> The datasheet (and you) claimed that it was a single chip. > >> >NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution... >> >> But then you kept saying "on chip", as does the datasheet. It's not. >> It's a kludge. > >One chip, with two dice. The flash is useful as a read-mainly store, so the odd >mounting makes some sense. It doesn't NEED heatsinking, or lots of >wire connection. No, one module with two chips. AKA (a poorly done) MCM (multi-chip module). >I'm uncertain what "it's a kludge" signifies. Does this relate to your filing system >"put this in the folder marked KLUDGE"? >Folders marked "miscellaneous' don't make sense either. No, this part goes into my recycle bin.
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| From | whit3rd <whit3rd@gmail.com> |
|---|---|
| Date | 2017-06-01 20:10 -0700 |
| Message-ID | <84796ee2-6a32-4c8e-984a-031f5b022e88@googlegroups.com> |
| In reply to | #462616 |
On Thursday, June 1, 2017 at 3:40:54 PM UTC-7, k...@notreal.com wrote: > On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: [about flash piggybacked on CPU die] > >> ... The whole idea is goofy. > > > >why? > > 1. It's a kludge A 'kludge' like adding another level of cache? When the manufacturer does it for you, you TAKE it and enjoy. Intel's Pentiums got more useful when they went to the Pentium Pro and various other multichip modules. > 2. SRAM is expensive/Flash is cheap Only in mass production. The flash requires more masks, and odd thin oxides with steps (for the floating gates) that can be omitted from a CPU. SRAM is identical to other CPU logic and registers, no extra masks or process steps. If you already have a FLASH production line, it makes sense to multipurpose its chip output for other products. > 3. Faster uCs are available, if necessary ?so? > 4. Off-chip flash is trivial and incredibly cheap. But, if there's enough ON-chip flash, some customers will pay to avoid the 'extra part'. Low power dissipation in the flash chip makes it a reasonable packaging decision. > Bottom line: it's a solution looking for a problem. It's an affordable upgrade from a bare-bones CPU, and when a design gets to the find-more-resources stage, this can be an easy sale. It makes business sense. It makes extra-special sense when the unexpected problem arises. That's happened to me, once or twice.
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| From | klaus.kragelund@gmail.com |
|---|---|
| Date | 2017-06-02 01:22 -0700 |
| Message-ID | <01df31f7-e007-47c6-9552-920417b5407c@googlegroups.com> |
| In reply to | #462646 |
On Friday, 2 June 2017 05:11:10 UTC+2, whit3rd wrote: > On Thursday, June 1, 2017 at 3:40:54 PM UTC-7, k...@notreal.com wrote: > > On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > > <langwadt@fonz.dk> wrote: > > > > >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: > > [about flash piggybacked on CPU die] > > > >> ... The whole idea is goofy. > > > > > >why? > > > > 1. It's a kludge > > A 'kludge' like adding another level of cache? When the manufacturer does it > for you, you TAKE it and enjoy. Intel's Pentiums got more useful when they > went to the Pentium Pro and various other multichip modules. > > > 2. SRAM is expensive/Flash is cheap > > Only in mass production. The flash requires more masks, and odd thin oxides > with steps (for the floating gates) that can be omitted from a CPU. > SRAM is identical to other CPU logic and registers, no extra masks or process steps. > If you already have a FLASH production line, it makes sense to multipurpose its > chip output for other products. > > > 3. Faster uCs are available, if necessary > ?so? > > > 4. Off-chip flash is trivial and incredibly cheap. > > But, if there's enough ON-chip flash, some customers will pay to avoid the 'extra part'. > Low power dissipation in the flash chip makes it a reasonable packaging decision. > > > Bottom line: it's a solution looking for a problem. > > It's an affordable upgrade from a bare-bones CPU, and when a design > gets to the find-more-resources stage, this can be an easy sale. It makes business > sense. It makes extra-special sense when the unexpected problem arises. > > That's happened to me, once or twice. Yes, exactly. And when before in history did you have the opportunity to have a almost real second source for a microcontroller, like here for the STM32/GD32 You have to go back to the 8051 I guess Cheers Klaus
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