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Running out of ideas: stability, bootstrap

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  Running out of ideas: stability, bootstrap Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-05-28 17:11 +0200
    Re: Running out of ideas: stability, bootstrap bitrex <bitrex@de.lete.earthlink.net> - 2017-05-28 12:09 -0400
      Re: Running out of ideas: stability, bootstrap Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-05-28 23:01 +0200
        Re: Running out of ideas: stability, bootstrap Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2017-05-28 14:30 -0700
          Re: Running out of ideas: stability, bootstrap Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-05-28 23:56 +0200
            Re: Running out of ideas: stability, bootstrap Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2017-05-28 15:08 -0700
    Re: Running out of ideas: stability, bootstrap John Larkin <jjlarkin@highlandtechnology.com> - 2017-05-28 09:46 -0700
      Re: Running out of ideas: stability, bootstrap Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-05-28 22:09 +0200
        Re: Running out of ideas: stability, bootstrap Joerg <news@analogconsultants.com> - 2017-05-29 07:13 -0700
          Re: Running out of ideas: stability, bootstrap dagmargoodboat@yahoo.com - 2017-05-29 20:56 -0700
            Re: Running out of ideas: stability, bootstrap Winfield Hill <hill@rowland.harvard.edu> - 2017-05-30 03:55 -0700
              Re: Running out of ideas: stability, bootstrap Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-05-30 15:53 +0200
                Re: Running out of ideas: stability, bootstrap dagmargoodboat@yahoo.com - 2017-05-30 10:42 -0700
    Re: Running out of ideas: stability, bootstrap bitrex <bitrex@de.lete.earthlink.net> - 2017-05-29 08:38 -0400
      Re: Running out of ideas: stability, bootstrap bitrex <bitrex@de.lete.earthlink.net> - 2017-05-29 08:40 -0400
      Re: Running out of ideas: stability, bootstrap Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-05-30 16:51 +0200
    Re: Running out of ideas: stability, bootstrap Winfield Hill <hill@rowland.harvard.edu> - 2017-05-29 07:36 -0700
      Re: Running out of ideas: stability, bootstrap bitrex <bitrex@de.lete.earthlink.net> - 2017-05-29 11:20 -0400
        Re: Running out of ideas: stability, bootstrap Jan Panteltje <pNa0nStpealmtje@yahoo.com> - 2017-05-29 15:36 +0000
          Re: Running out of ideas: stability, bootstrap bitrex <bitrex@de.lete.earthlink.net> - 2017-05-29 11:44 -0400
            Re: Running out of ideas: stability, bootstrap bitrex <bitrex@de.lete.earthlink.net> - 2017-05-29 11:53 -0400
            Re: Running out of ideas: stability, bootstrap Jan Panteltje <pNa0nStpealmtje@yahoo.com> - 2017-05-29 17:01 +0000
          Re: Running out of ideas: stability, bootstrap Winfield Hill <hill@rowland.harvard.edu> - 2017-05-29 08:46 -0700
            Re: Running out of ideas: stability, bootstrap Jan Panteltje <pNa0nStpealmtje@yahoo.com> - 2017-05-29 16:56 +0000
        Re: Running out of ideas: stability, bootstrap dagmargoodboat@yahoo.com - 2017-05-29 21:12 -0700

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#462075 — Running out of ideas: stability, bootstrap

Hi, all,

we had a bank holiday here, nicely positioned close to
the weekend and I took the free time to play with my
multi-IF3601 low noise amplifier.

That was not so funny because it features a negative
input impedance over most frequencies, so with
a suitable inductance on the input it makes a stable
oscillator.

Some observations:

- Zin is negative also with the feedback loop cut

- Choice op op amp does not matter: ADA4898 vs. THS4022

- There is no coupling via the bias system; base bias
   used to have a 2nd current source that shared the
   BAV99 string; that could produce startup problems (solved)

- type of cascode transistor did not make much of a difference,
   using an Infineon BFQ19S instead of FZT851/ZXT690B looked
   slightly better, but not good enough.

- Leaving the cascode transistor out remedied the situation,
   but I need the cascode transistor to introduce the bootstrap
   to eliminate Cgd of the paralleled FETs.

- The THS4022 suppresses the Miller effect quite nicely at
   least to 100 KHz, but the unmultiplied Cgate-drain is still
   easily a nF of more.

- The obvious solution of gate stoppers does not make sense
   because of the noise. A resistor in the base lead of the
   cascode makes things worse; 6R8 between the drains and
   the cascode emitter made no difference. (could not use
   more without messing up the DC operating point, it also
   would interfere with the bootstrap)

- ferrite beads in the gates do exactly nothing.

circuit snippet is at
< 
https://www.flickr.com/photos/137684711@N07/34904768906/in/album-72157682404684680/ 
 >

   Currently, there are 4 FETs in parallel.

Does the combined expertise of the group have any idea on
how to stabilize the cascode or an alternative way to
introduce the bootstrap?

Best regards,

Gerhard

[toc] | [next] | [standalone]

#462079

On 05/28/2017 11:11 AM, Gerhard Hoffmann wrote:
> Hi, all,
> 
> we had a bank holiday here, nicely positioned close to
> the weekend and I took the free time to play with my
> multi-IF3601 low noise amplifier.
> 
> That was not so funny because it features a negative
> input impedance over most frequencies, so with
> a suitable inductance on the input it makes a stable
> oscillator.
> 
> Some observations:
> 
> - Zin is negative also with the feedback loop cut
> 
> - Choice op op amp does not matter: ADA4898 vs. THS4022
> 
> - There is no coupling via the bias system; base bias
>    used to have a 2nd current source that shared the
>    BAV99 string; that could produce startup problems (solved)
> 
> - type of cascode transistor did not make much of a difference,
>    using an Infineon BFQ19S instead of FZT851/ZXT690B looked
>    slightly better, but not good enough.
> 
> - Leaving the cascode transistor out remedied the situation,
>    but I need the cascode transistor to introduce the bootstrap
>    to eliminate Cgd of the paralleled FETs.
> 
> - The THS4022 suppresses the Miller effect quite nicely at
>    least to 100 KHz, but the unmultiplied Cgate-drain is still
>    easily a nF of more.
> 
> - The obvious solution of gate stoppers does not make sense
>    because of the noise. A resistor in the base lead of the
>    cascode makes things worse; 6R8 between the drains and
>    the cascode emitter made no difference. (could not use
>    more without messing up the DC operating point, it ahlso
>    would interfere with the bootstrap)
> 
> - ferrite beads in the gates do exactly nothing.
> 
> circuit snippet is at
> < 
> https://www.flickr.com/photos/137684711@N07/34904768906/in/album-72157682404684680/ 
>  >
> 
>    Currently, there are 4 FETs in parallel.
> 
> Does the combined expertise of the group have any idea on
> how to stabilize the cascode or an alternative way to
> introduce the bootstrap?
> 
> Best regards,
> 
> Gerhard

Did you check out some of the ideas guys had on the thread "Fast buffer 
idea?"

As JL might say, this cascode bootstrapping arrangement looks way too 
complicated and uses too many parts. I don't completely understand it. 
Why not drive the boostrapping transistor from its base?

:-( the mindset is catchy apparently...

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#462119

Am 28.05.2017 um 18:09 schrieb bitrex:


> Did you check out some of the ideas guys had on the thread "Fast buffer 
> idea?"
> 
> As JL might say, this cascode bootstrapping arrangement looks way too 
> complicated and uses too many parts. I don't completely understand it. 
> Why not drive the boostrapping transistor from its base?

The bootstrapping is not yet included in the board; only the
cascode as a precondition.  The cascode also gave quite a rise
in bandwidth when I used the ADA4898 and better Miller killing
abilities at up to 160 mA.

I first wanted to drive the base
from a leftover FET opamp used as a follower; OTOH the same
voltage is available at the sources of the IF3601; a 0.1 Ohm
source resistor looks impressively low impedance, but at this
point the signal has already travelled through the cascode
and the THS4022 op amp, that introduces unwelcome dependencies.

The 0.1 Ohms look small and everything seems common source,
but the feedback through the op amp makes it behave like a high
impedance current source from the FET's point of view. The
source follows the gate quite closely after all.

The drain looks into ~ 0 Ohms of the cascode emitter, and if
the signal fed back from the op amp has the right phase, it
looks capacitively for the FET. That alone could provide
the negative input impedance (like in a standard VHF VCO,
aka capacitivly loaded follower).

Only the fact that Zin is still negative when I cut the
feedback makes me assume that the cascode transistor is the
culprit.

The 0.1 Ohm source resistors btw were necessary with 8
parallel FETs, or they would cost 10 pV/rtHz in simulation
when you are just at +/- 100 pV/rtHz.


> :-( the mindset is catchy apparently...

Cheers, Gerhard

(got a nice Tempranillo)

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#462125

On Sun, 28 May 2017 23:01:17 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

>Am 28.05.2017 um 18:09 schrieb bitrex:
>
>
>> Did you check out some of the ideas guys had on the thread "Fast buffer 
>> idea?"
>> 
>> As JL might say, this cascode bootstrapping arrangement looks way too 
>> complicated and uses too many parts. I don't completely understand it. 
>> Why not drive the boostrapping transistor from its base?
>
>The bootstrapping is not yet included in the board; only the
>cascode as a precondition.  The cascode also gave quite a rise
>in bandwidth when I used the ADA4898 and better Miller killing
>abilities at up to 160 mA.
>
>I first wanted to drive the base
>from a leftover FET opamp used as a follower; OTOH the same
>voltage is available at the sources of the IF3601; a 0.1 Ohm
>source resistor looks impressively low impedance, but at this
>point the signal has already travelled through the cascode
>and the THS4022 op amp, that introduces unwelcome dependencies.
>
>The 0.1 Ohms look small and everything seems common source,
>but the feedback through the op amp makes it behave like a high
>impedance current source from the FET's point of view. The
>source follows the gate quite closely after all.
>
>The drain looks into ~ 0 Ohms of the cascode emitter, and if
>the signal fed back from the op amp has the right phase, it
>looks capacitively for the FET. That alone could provide
>the negative input impedance (like in a standard VHF VCO,
>aka capacitivly loaded follower).
>
>Only the fact that Zin is still negative when I cut the
>feedback makes me assume that the cascode transistor is the
>culprit.
>
>The 0.1 Ohm source resistors btw were necessary with 8
>parallel FETs, or they would cost 10 pV/rtHz in simulation
>when you are just at +/- 100 pV/rtHz.
>
>
>> :-( the mindset is catchy apparently...
>
>Cheers, Gerhard
>
>(got a nice Tempranillo)

Though it says C4, dni, is it there?  Maybe the capacitance at that
node is making Q3 unstable?
		
                                        ...Jim Thompson
-- 
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

     Thinking outside the box... producing elegant solutions.

"It is not in doing what you like, but in liking what you do that
is the secret of happiness."  -James Barrie

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#462128

Am 28.05.2017 um 23:30 schrieb Jim Thompson:

> 
> Though it says C4, dni, is it there?  Maybe the capacitance at that
> node is making Q3 unstable?

No, it is not there, just an opportunity so solder something.

But adding a capacitor of 150p between base and C of the cascode
improves the situation slightly, although not enough, and it looks
wrong.

cheers, Gerhard

(getting tired slowly because of said Tempranillo :.)

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#462129

On Sun, 28 May 2017 23:56:41 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

>Am 28.05.2017 um 23:30 schrieb Jim Thompson:
>
>> 
>> Though it says C4, dni, is it there?  Maybe the capacitance at that
>> node is making Q3 unstable?
>
>No, it is not there, just an opportunity so solder something.
>
>But adding a capacitor of 150p between base and C of the cascode
>improves the situation slightly, although not enough, and it looks
>wrong.

Strange.

>
>cheers, Gerhard
>
>(getting tired slowly because of said Tempranillo :.)

Enjoy >:-}
		
                                        ...Jim Thompson
-- 
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

     Thinking outside the box... producing elegant solutions.

"It is not in doing what you like, but in liking what you do that
is the secret of happiness."  -James Barrie

[toc] | [prev] | [next] | [standalone]

#462085

On Sun, 28 May 2017 17:11:52 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

>Hi, all,
>
>we had a bank holiday here, nicely positioned close to
>the weekend and I took the free time to play with my
>multi-IF3601 low noise amplifier.
>
>That was not so funny because it features a negative
>input impedance over most frequencies, so with
>a suitable inductance on the input it makes a stable
>oscillator.
>
>Some observations:
>
>- Zin is negative also with the feedback loop cut
>
>- Choice op op amp does not matter: ADA4898 vs. THS4022
>
>- There is no coupling via the bias system; base bias
>   used to have a 2nd current source that shared the
>   BAV99 string; that could produce startup problems (solved)
>
>- type of cascode transistor did not make much of a difference,
>   using an Infineon BFQ19S instead of FZT851/ZXT690B looked
>   slightly better, but not good enough.
>
>- Leaving the cascode transistor out remedied the situation,
>   but I need the cascode transistor to introduce the bootstrap
>   to eliminate Cgd of the paralleled FETs.
>
>- The THS4022 suppresses the Miller effect quite nicely at
>   least to 100 KHz, but the unmultiplied Cgate-drain is still
>   easily a nF of more.
>
>- The obvious solution of gate stoppers does not make sense
>   because of the noise. A resistor in the base lead of the
>   cascode makes things worse; 6R8 between the drains and
>   the cascode emitter made no difference. (could not use
>   more without messing up the DC operating point, it also
>   would interfere with the bootstrap)
>
>- ferrite beads in the gates do exactly nothing.
>
>circuit snippet is at
>< 
>https://www.flickr.com/photos/137684711@N07/34904768906/in/album-72157682404684680/ 
> >
>
>   Currently, there are 4 FETs in parallel.
>
>Does the combined expertise of the group have any idea on
>how to stabilize the cascode or an alternative way to
>introduce the bootstrap?
>
>Best regards,
>
>Gerhard
>
>
>

Over what frequency range is the Zin negative?

Where does GATE_BIAS come from?

How is this physically assembled?


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#462108

Am 28.05.2017 um 18:46 schrieb John Larkin:

> 
> Over what frequency range is the Zin negative?

The network analyzer starts officially at 300 KHz,
non-guaranteed at 150KHz. At 150 KHz Zin is already
negative. It seems, at about 10 MHz everything is
running out of steam, so it stops being offensive.

Every impedance inside the circle that goes through 0
has a positive real part. Everything on the circle
through 0 has zero Ohms, only LC.
Everything outside of that circle has a negative
real part.
The Smith diagram is in the same photo album.

There are no complaints by LTspice.
In a very old version of Genesys, I get about the same
behavior regarding Zin. But I could not make the
bias loop converge, so setting the operating point
is clumsy.


> Where does GATE_BIAS come from?

That comes from an integrator. I have added that
part of the circuit. Since the 30uF input capacitance
* 66Meg bias resistor takes an eternity to settle,
I have added a window comparator & analog switch to
reduce the bias resistor by paralleling 4Meg7.
That works.

> 
> How is this physically assembled?

It is all on a small dual-sided circuit board.
Pic included. It does no longer look that tidy.  :-)

< https://www.flickr.com/photos/137684711@N07/albums/72157682404684680 >

and the pics left/right of it.

cheers,

Gerhard

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#462161

On 2017-05-28 13:09, Gerhard Hoffmann wrote:
> Am 28.05.2017 um 18:46 schrieb John Larkin:
>
>>
>> Over what frequency range is the Zin negative?
>
> The network analyzer starts officially at 300 KHz,
> non-guaranteed at 150KHz. At 150 KHz Zin is already
> negative. It seems, at about 10 MHz everything is
> running out of steam, so it stops being offensive.
>
> Every impedance inside the circle that goes through 0
> has a positive real part. Everything on the circle
> through 0 has zero Ohms, only LC.
> Everything outside of that circle has a negative
> real part.
> The Smith diagram is in the same photo album.
>
> There are no complaints by LTspice.
> In a very old version of Genesys, I get about the same
> behavior regarding Zin. But I could not make the
> bias loop converge, so setting the operating point
> is clumsy.
>
>
>> Where does GATE_BIAS come from?
>
> That comes from an integrator. I have added that
> part of the circuit. Since the 30uF input capacitance
> * 66Meg bias resistor takes an eternity to settle,
> I have added a window comparator & analog switch to
> reduce the bias resistor by paralleling 4Meg7.
> That works.
>
>>
>> How is this physically assembled?
>
> It is all on a small dual-sided circuit board.
> Pic included. It does no longer look that tidy.  :-)
>
> < https://www.flickr.com/photos/137684711@N07/albums/72157682404684680 >
>
> and the pics left/right of it.
>

The 17.6pF cap could perform better if it had a flag in the Borussia 
Dortmund colors black and yellow :-)

Just curious, shouldn't there be a cap to ground at the base of Q3 and 
maybe also Q2?

-- 
Regards, Joerg

http://www.analogconsultants.com/

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#462254

On Monday, May 29, 2017 at 10:13:51 AM UTC-4, Joerg wrote:
> On 2017-05-28 13:09, Gerhard Hoffmann wrote:
> > Am 28.05.2017 um 18:46 schrieb John Larkin:
> >
> >>
> >> Over what frequency range is the Zin negative?
> >
> > The network analyzer starts officially at 300 KHz,
> > non-guaranteed at 150KHz. At 150 KHz Zin is already
> > negative. It seems, at about 10 MHz everything is
> > running out of steam, so it stops being offensive.
> >
> > Every impedance inside the circle that goes through 0
> > has a positive real part. Everything on the circle
> > through 0 has zero Ohms, only LC.
> > Everything outside of that circle has a negative
> > real part.
> > The Smith diagram is in the same photo album.
> >
> > There are no complaints by LTspice.
> > In a very old version of Genesys, I get about the same
> > behavior regarding Zin. But I could not make the
> > bias loop converge, so setting the operating point
> > is clumsy.
> >
> >
> >> Where does GATE_BIAS come from?
> >
> > That comes from an integrator. I have added that
> > part of the circuit. Since the 30uF input capacitance
> > * 66Meg bias resistor takes an eternity to settle,
> > I have added a window comparator & analog switch to
> > reduce the bias resistor by paralleling 4Meg7.
> > That works.
> >
> >>
> >> How is this physically assembled?
> >
> > It is all on a small dual-sided circuit board.
> > Pic included. It does no longer look that tidy.  :-)
> >
> > < https://www.flickr.com/photos/137684711@N07/albums/72157682404684680 >
> >
> > and the pics left/right of it.
> >
> 
> The 17.6pF cap could perform better if it had a flag in the Borussia 
> Dortmund colors black and yellow :-)
> 
> Just curious, shouldn't there be a cap to ground at the base of Q3 and 
> maybe also Q2?

+1 on Q3.  I'd suggest moving the aptly-named C666 to Q3's base.
Current-source Q2 is bypassed to +10V, so no problem there.

I don't trust 2.7V zeners or emitter-followers with big base resistors
here. Moving C666 should reveal whether this node is the source of the
weirdness.

Cheers,
James Arthur

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#462277

dagmargoodboat@yahoo.com wrote...
>
> I don't trust 2.7V zeners or emitter-followers with
> big base resistors here. Moving C666 should reveal
> whether this node is the source of the weirdness.

 Indeed.  Zin for the cascode Q3 emitter is 100/beta
 and beta = fT/f, which is 13 at 10MHz for FZT851, or
 Zin = 7.7 ohms at 10MHz, rising with f, acting as
 nasty 207nH inductor.  Not to mention a 1.3nV.rt-Hz
 voltage-noise source.   Axe that 100 ohms.


-- 
 Thanks,
    - Win

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#462291

Am 30.05.2017 um 12:55 schrieb Winfield Hill:
> dagmargoodboat@yahoo.com wrote...
>>
>> I don't trust 2.7V zeners or emitter-followers with
>> big base resistors here. Moving C666 should reveal
>> whether this node is the source of the weirdness.
> 
>   Indeed.  Zin for the cascode Q3 emitter is 100/beta
>   and beta = fT/f, which is 13 at 10MHz for FZT851, or
>   Zin = 7.7 ohms at 10MHz, rising with f, acting as
>   nasty 207nH inductor.  Not to mention a 1.3nV.rt-Hz
>   voltage-noise source.   Axe that 100 ohms.

Yes, the 100R are just there to check the sensitivity.
The bad thing is that even for a zero Ohm resistor, the
S11 comes only a bit closer to the circle that
encloses the positive resistance region, but it still
takes a walk outside.

But I need at least a few Ohms so I can insert the
buffered input voltage for the bootstrap.

The entire bias chain has no impact on the total noise,
even including the Zener and with absolutely minimum
decoupling.


Here is a stripped down version in LTspice:

screendump:
< 
https://www.flickr.com/photos/137684711@N07/34987159135/in/album-72157682404684680/ 
 >

noise results, including some contributors:
<https://www.flickr.com/photos/137684711@N07/34823792822/in/album-72157682404684680/ 
  >

It seems that above 1 MHz, the active loads quickly becomes ineffective
in suppressing the VCC noise. But 1 MHz BW is enough.

regards, Gerhard


---- >% ---- >% ---- >% ---- >% ---- >% ---- >% ---- >% ---- >%

Version 4
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WIRE -176 688 -176 512
WIRE 64 784 64 736
WIRE 400 784 256 784
WIRE 496 784 496 752
WIRE 496 784 464 784
WIRE -384 832 -384 768
WIRE -176 832 -176 768
WIRE 384 864 304 864
WIRE 496 864 496 784
WIRE 496 864 464 864
WIRE -384 880 -384 832
WIRE 304 912 304 864
WIRE 448 960 416 960
WIRE 480 960 448 960
WIRE -384 992 -384 960
WIRE 416 992 416 960
WIRE 496 1008 496 864
WIRE 496 1008 448 1008
WIRE -176 1024 -176 832
WIRE 256 1024 256 784
WIRE 256 1024 -176 1024
WIRE 304 1024 304 976
WIRE 304 1024 256 1024
WIRE 384 1024 304 1024
WIRE 496 1040 448 1040
WIRE 352 1088 320 1088
WIRE 416 1088 416 1056
WIRE 416 1088 352 1088
FLAG 240 1088 0
FLAG -336 256 0
FLAG -384 992 0
FLAG -144 512 vgat
FLAG 48 432 drain
FLAG 496 208 op_out
FLAG -336 -256 vcc
FLAG -64 240 Vbase
FLAG 448 960 vcc
FLAG 352 1088 vee
FLAG -176 832 bias
FLAG 144 544 source
FLAG -384 832 vgen
FLAG -464 512 0
FLAG 432 176 vee
FLAG -112 32 center
FLAG -208 400 0
FLAG 128 -32 0
FLAG 496 1040 0
FLAG -240 96 0
FLAG 64 784 0
FLAG 464 32 vcc
FLAG -160 400 0
FLAG 624 272 0
FLAG 688 320 0
FLAG 688 224 0
SYMBOL voltage -336 160 R0
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 -52 151 VTop 2
SYMATTR InstName V1
SYMATTR Value 9.8
SYMATTR SpiceLine Rser=0.001
SYMBOL voltage -384 864 R0
WINDOW 123 34 174 Left 2
WINDOW 39 24 132 Left 2
SYMATTR Value2 AC 1 1
SYMATTR SpiceLine Rser=0
SYMATTR InstName V2
SYMATTR Value SINE(0.0 0.005 1000 0 0 0)
SYMBOL voltage 224 1088 R270
WINDOW 123 24 160 Left 2
WINDOW 39 -27 -60 Left 2
WINDOW 3 -2 -31 Left 2
WINDOW 0 -16 -106 Left 2
SYMATTR SpiceLine Rser=0.1
SYMATTR Value 4.98
SYMATTR InstName V4
SYMBOL res 160 608 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R20
SYMATTR Value 100
SYMBOL res 48 640 R0
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SYMBOL cap -240 496 R90
WINDOW 0 0 32 VBottom 2
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SYMATTR Value 60meg
SYMBOL njf 0 448 R0
WINDOW 0 -21 39 Left 2
WINDOW 3 -30 101 Left 2
WINDOW 123 -34 130 Left 2
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SYMATTR Value IF3601
SYMATTR Value2 m=4
SYMBOL res -368 496 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
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SYMATTR Value 9999Meg
SYMBOL res 512 768 R180
WINDOW 0 36 76 Left 2
WINDOW 3 -77 43 Left 2
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SYMATTR Value 10meg
SYMBOL Opamps\\LT1792 416 960 M0
SYMATTR InstName U5A
SYMBOL e -336 16 R0
SYMATTR InstName E1
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SYMBOL res -480 -48 R0
SYMATTR InstName R1
SYMATTR Value 60
SYMBOL res 464 528 R90
WINDOW 0 0 56 VBottom 2
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SYMATTR InstName C5
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WINDOW 3 32 56 VTop 2
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SYMBOL res 480 848 R90
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WINDOW 3 32 56 VTop 2
SYMATTR InstName R18
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SYMBOL cap 416 -32 R90
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SYMBOL zener -192 368 R180
WINDOW 0 24 64 Left 2
WINDOW 3 -46 -65 Left 2
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SYMATTR Value BZX84-C2v7
SYMBOL pnp 112 -96 R180
SYMATTR InstName Q1
SYMATTR Value ZTX951
SYMBOL res 32 -336 R0
SYMATTR InstName R1005
SYMATTR Value 33
SYMBOL res 112 -128 R0
SYMATTR InstName R1006
SYMATTR Value 1k
SYMBOL diode 112 -256 R0
WINDOW 0 46 -11 Left 2
WINDOW 3 40 48 Left 2
WINDOW 123 48 21 Left 2
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SYMATTR Value2 n=5
SYMBOL res 480 -112 R90
WINDOW 0 0 56 VBottom 2
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SYMATTR InstName R17
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SYMBOL res -176 112 R0
WINDOW 3 38 71 Left 2
SYMATTR InstName R1003
SYMATTR Value 240
SYMBOL cap 464 768 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C8
SYMATTR Value 2n2
SYMBOL cap -256 32 R0
WINDOW 3 42 43 Left 2
SYMATTR Value 47µ
SYMATTR InstName C1001
SYMATTR SpiceLine Rser=0.1
SYMBOL res -64 224 R90
WINDOW 0 66 -8 VBottom 2
WINDOW 3 40 56 VTop 2
SYMATTR InstName R1414
SYMATTR Value 0.1
SYMBOL cap 320 528 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 1p
SYMBOL cap 240 -272 R0
SYMATTR InstName C1004
SYMATTR Value 680µ
SYMBOL current -160 -224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value 10m
SYMBOL Opamps\\opamp2 432 32 R0
SYMATTR InstName U1A
SYMATTR Value ths4021
SYMBOL res -400 672 R0
SYMATTR InstName R1000
SYMATTR Value 0.01
SYMBOL cap -176 304 R0
WINDOW 3 42 43 Left 2
WINDOW 0 36 69 Left 2
SYMATTR Value 47µ
SYMATTR InstName C1000
SYMATTR SpiceLine Rser=0.1
SYMBOL npn -16 192 R0
SYMATTR InstName Q3
SYMATTR Value ZTX851
TEXT 168 336 Left 2 !.noise V(op_out) V2 dec 1000 100 1E7
TEXT 168 304 Left 2 !;ac dec 1000 10m 100Meg
TEXT -496 -80 Left 2 ;1nV/RtHz noise plus\njust non-zero offset
TEXT -376 -352 Left 2 ;Vcc + E1 * 1n VRtHz noise
TEXT 168 280 Left 2 !;tran 500s
TEXT 168 248 Left 2 !.op
TEXT 168 368 Left 2 !;.include d:\\lib\\spice\\ghf_spice_lib.txt
TEXT -1528 -560 Left 2 
!*******************************************************************************\n\n* 
THS4021 SUBCIRCUIT\n\n* HIGH SPEED MONLITHIC OPERATIONAL AMPLIFIER \n\n* 
WRITTEN 1/6/99\n\n* NULL PINS ARE NOT MODELED\n\n* TEMPLATE=X^@REFDES 
%IN+ %IN- %VCC+ %VCC- %OUT @MODEL\n\n* CONNECTIONS:      NON-INVERTING 
INPUT\n\n*                   | INVERTING INPUT\n\n*                   | 
| POSITIVE POWER SUPPLY\n\n*                   | | | NEGATIVE POWER 
SUPPLY\n\n*                   | | | | OUTPUT\n\n*                   | | 
| | | \n\n*                   | | | | | \n\n*                   | | | | 
| \n\n.SUBCKT THS4021     1 2 3 4 5 \n\n*\n\n* INPUT *\n\nQ1         33 
1 17 NPN_IN 1\n\nQ2         34 2 17 NPN_IN 1\n\n\n* PROTECTION DIODES 
*\n\nD2         5 3 D1N \n\nD1         4 5 D1N \n\nD4         4 2 D1N 
\n\nD6         4 1 D1N \n\nD5         1 3 D1N \n\nD8         22 1 D1N 
\n\nD7         22 2 D1N \n\nD3         2 3 D1N \n\n\n* SECOND STAGE 
*\n\nQ3         08 Vref 33 PNP 0.5\n\nQ6         10 08 09 NPN 0.25\n\nQ4 
         10 Vref 34 PNP 0.5\n\nQ5         08 09 11 NPN 1\n\nQ7 
09 09 12 NPN 1\n\nCc         0 10  Ct 4p  \n\nR3         4 11  333 
\n\nR4         4 12  333\n\n\n* SLEW RATE ENHANCEMENT *\n\nG6         0 
10 1 2 0.75e-3\n\n\n\n\n* HIGH FREQUENCY SHAPING *\n\nLhf         18 19 
23n  \n\nRhf         13 19  25  \n\nChf         0  13  9p  \n\nEhf 
   18 0 10 0 1\n\n\n* OUTPUT *\n\nQ8         13 13 35 PNP 1\n\nQ9 
  13 13 14 NPN 1\n\nQ10         3 35 15 NPN 12\n\nQ11         4 14 16 
PNP 14\n\nR5         20 15  10  \n\nR7         16 20  10\n\n\n\n\n* 
COMPLEX OUTPUT IMPEDANCE *\n\nR8         32 20  10  \n\nR9         31 20 
  10 \n\nL1         31 5  10n  \n\nC1         32 5  25p  \n\n\n\n\n* 
BIAS SOURCES *\n\nG1         3 33 3 4 6.3e-6 \n\nG2         3 34 3 4 
6.3e-6\n\nG3         0 35 3 4 5.4e-6\n\nG4         17 4 3 4 
5.25e-6\n\nG5         14 0 3 4 6.1e-6\n\nI1         3 33  DC 1.3e-3 
\n\nI2         3 34  DC 1.3e-3 \n\nI3         0 35  DC 1.5e-3 \n\nI4 
     17 4  DC 1.3e-3 \n\nI5         14 0  DC 1.7e-3 \n\nV1         3 
Vref DC 2 \n\n\n* MODELS *\n\n.MODEL NPN_IN NPN\n\n+ IS=170E-18 BF=400 
NF=1 VAF=100 IKF=0.0389 ISE=7.6E-18\n\n+ NE=1.13489 BR=1.11868 NR=1 
VAR=4.46837 IKR=8 ISC=8E-15\n\n+ NC=1.8 RB=25 RE=0.1220 RC=20 
CJE=120.2E-15 VJE=1.0888 MJE=0.381406\n\n+ VJC=0.589703 MJC=0.265838 
FC=0.1 CJC=133.8E-15 XTF=272.204 TF=12.13E-12\n\n+ VTF=10 ITF=0.147 
TR=3E-09 XTB=1 XTI=5 KF=2.5E-13\n\n\n.MODEL NPN NPN\n\n+ IS=170E-18 
BF=100 NF=1 VAF=100 IKF=0.0389 ISE=7.6E-18\n\n+ NE=1.13489 BR=1.11868 
NR=1 VAR=4.46837 IKR=8 ISC=8E-15\n\n+ NC=1.8 RB=250 RE=0.1220 RC=200 
CJE=120.2E-15 VJE=1.0888 MJE=0.381406\n\n+ VJC=0.589703 MJC=0.265838 
FC=0.1 CJC=133.8E-15 XTF=272.204 TF=12.13E-12\n\n+ VTF=10 ITF=0.147 
TR=3E-09 XTB=1 XTI=5\n\n\n.MODEL PNP PNP\n\n+ IS=296E-18 BF=100 NF=1 
VAF=100 IKF=0.021 ISE=494E-18\n\n+ NE=1.49168 BR=0.491925 NR=1 
VAR=2.35634 IKR=8 ISC=8E-15\n\n+ NC=1.8 RB=250 RE=0.1220 RC=200 
CJE=120.2E-15 VJE=0.940007 MJE=0.55\n\n+ VJC=0.588526 MJC=0.55 FC=0.1 
CJC=133.8E-15 XTF=141.135 TF=12.13E-12\n\n+ VTF=6.82756 ITF=0.267 
TR=3E-09 XTB=1 XTI=5\n\n\n.MODEL Ct CAP TC1=-0.0025\n\n\n.MODEL D1N D 
IS=10E-15 N=1.836 ISR=1.565e-9 IKF=.04417 BV=30 IBV=10E-6 RS=45\n\n+ 
TT=11.54E-9 CJO=2E-12 VJ=.5 M=.3333\n\n\n.ENDS
TEXT -24 -352 Left 2 ;active load needed for PSSR
TEXT -384 1272 Left 2 !*ZETEX  ZTX851 Spice model   Last revision 
21/1/93  (C)  1993 ZETEX PLC\n\n.MODEL ZTX851 NPN IS =1.0085E-12 NF 
=1.0001 BF =240 IKF=5.1 VAF=158\n\n+             ISE=2E-13 NE =1.38 NR 
=0.9988 BR =110 IKR=5.5 VAR=46 \n\n+             ISC=4.6515E-13 NC 
=1.334 RB =0.025 RE =0.018 RC =0.015 \n\n+             CJC=155E-12 
MJC=0.4348 VJC=0.6477 CJE=1.05E-9 \n\n+             TF =0.79E-9 TR 
=24E-9\n \n.model if3601 njf beta=260m lambda=1m rd=40m rs=40m is=0.05n 
cgd=1200p m=0.5 cgs=600p\n+ pb=0.75 kf=1e-18 b=1.8 vto=-1.5\n \n 
\n.model bzx84-c2v7 d(is=110.88e-18 n=.92657 rs=.85899 ikf=147.68 
cjo=344.69e-12 m=.31964\n+  vj=.72935 isr=1.5159e-6 bv=2.7639 
ibv=69.770e-3 tt=17.889e-9 vpk=2.7 mfg=philips type=zener)\n \n \n.model 
bav99s d(is=7.4960e-9 n=2.0077 rs=.80464 ikf=.1058 cjo=515.09e-15 m=.115 
vj=.6389 \n+ isr=1.4182e-9 nr=4.9950 bv=90.375 ibv=10 tt=2.1640e-9 
iave=0.2 vpk=75 mfg=philips type=silicon)\n \n.model ztx951 pnp 
is=1.3766e-12 nf=1.013 bf=187 ikf=5.0 vaf=66.3 ise=1.4e-13 ne=1.41 
nr=1.0099 \n+ br=56 ikr=0.9 var=33 isc=1.7e-12 nc=1.4 rb=0.029 re=0.020 
rc=0.0255 cjc=287e-12 mjc=0.4522\n+ vjc=0.4956 cje=1.15e-9 tf=0.83e-9 
tr=20e-9
TEXT 168 408 Left 2 !.savebias portable.bias internal
TEXT 176 440 Left 2 !;.loadbias portable.bias

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#462314

On Tuesday, May 30, 2017 at 9:54:13 AM UTC-4, Gerhard Hoffmann wrote:
> Am 30.05.2017 um 12:55 schrieb Winfield Hill:
> > dagmargoodboat@yahoo.com wrote...
> >>
> >> I don't trust 2.7V zeners or emitter-followers with
> >> big base resistors here. Moving C666 should reveal
> >> whether this node is the source of the weirdness.
> > 
> >   Indeed.  Zin for the cascode Q3 emitter is 100/beta
> >   and beta = fT/f, which is 13 at 10MHz for FZT851, or
> >   Zin = 7.7 ohms at 10MHz, rising with f, acting as
> >   nasty 207nH inductor.  Not to mention a 1.3nV.rt-Hz
> >   voltage-noise source.   Axe that 100 ohms.
> 
> Yes, the 100R are just there to check the sensitivity.
> The bad thing is that even for a zero Ohm resistor, the
> S11 comes only a bit closer to the circle that
> encloses the positive resistance region, but it still
> takes a walk outside.
> 
> But I need at least a few Ohms so I can insert the
> buffered input voltage for the bootstrap.

Thanks for the details.  In your original post, you wrote:

 "That was not so funny because it features a negative
  input impedance over most frequencies, so with
  a suitable inductance on the input it makes a stable
  oscillator."

If putting an inductor on the input makes an oscillator, this
can only mean that energy is being fed from the output back to
the input.

The two obvious paths for that are Cdg and Cgs.

You seem to have eliminated Cdg as a cause, by your report
that the negative resistance is relatively insensitive to
the cascode's base resistance.

Logically, this points suspicion at Cgs, a positive-feedback
capacitance famous for making BJTs into oscillators.

I'd suspect your feedback loop, injecting energy into the FET array's
source that couples through to its gate, except you've already reported
that the problem persists even with the feedback loop disabled.

This leaves the FETs themselves.

You could also test the possibility that Cgs feedthrough is the cause,
by temporarily lowering the operating current and disconnecting most
of the JFET array.

If 4 x Cgs is a problem, 1 x Cgs should be one-fourth as bad.

If you can identify the source of the problem, you'll be able
to devise a correction for it. (E.g., if this were r.f.,
neutralization.)

The frequency of oscillation for an input inductor L might give a
hint as to the value of any capacitance at play here.

Cheers,
James Arthur

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#462157

On 05/28/2017 11:11 AM, Gerhard Hoffmann wrote:
> Hi, all,
> 
> we had a bank holiday here, nicely positioned close to
> the weekend and I took the free time to play with my
> multi-IF3601 low noise amplifier.
> 
> That was not so funny because it features a negative
> input impedance over most frequencies, so with
> a suitable inductance on the input it makes a stable
> oscillator.
> 
> Some observations:
> 
> - Zin is negative also with the feedback loop cut

Which feedback loop? There are two that I see in the circuit as posted: 
the one driven by the FET source feeding the R17/R23 etc. RC network 
where U1A is acting as an inverting amplifier, and possibly some kind of 
integrator network off page used to generate the bias voltage for the 
FET gate.

> circuit snippet is at
> < 
> https://www.flickr.com/photos/137684711@N07/34904768906/in/album-72157682404684680/ 
> 
> 
>    Currently, there are 4 FETs in parallel.
> 
> Does the combined expertise of the group have any idea on
> how to stabilize the cascode or an alternative way to
> introduce the bootstrap?
> 
> Best regards,
> 
> Gerhard

I'm assuming the goal here is to build a low-noise source follower, with 
the output buffered by an op amp.

It looks like the non-inverting input of U1A is tied to a virtual 
ground, and the inverting input is tied to the collector of Q3, I'm 
guessing to try to use negative feedback to fix the collector voltage at 
4.57. But since Q3 is fed by current source Q2, the collector of Q3 
(test point P3) is a high-impedance node and so it seems to me that the 
only way the DC voltage there can be controlled is by U1A sensing the 
source voltage of the FET, through the R17/R23 network, and then around 
the loop through the integrator (not shown) back to the gate of the FET, 
if I'm understanding the circuit correctly.

The gain from the gate of the cascoded FET to the output of U1A isn't 
well-defined; from "its perspective" it looks like a current source 
loaded common-emitter amplifier feeding a transimpedance converter. It 
will be very large. Plus the phase shift from U1A and the integrator to 
the gate it sounds like a recipe for oscillation.

If I were dead-set on using a current source for the cascode collector 
load I think it would be better to let one op-amp section handle a 
feedback loop around the upper current source to set the DC bias at Q3's 
collector, and let U1A and the integrator just handle setting the FET's 
bias and the 0V DC level to the post amplifier. Delegate some 
responsibility...

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#462158

On 05/29/2017 08:38 AM, bitrex wrote:

> The gain from the gate of the cascoded FET to the output of U1A isn't 
> well-defined; from "its perspective" it looks like a current source 
> loaded common-emitter amplifier feeding a transimpedance converter.
Should be "from the gate of the FET to the output of U1A via the 
collector of the cascode"

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#462301

Am 29.05.2017 um 14:38 schrieb bitrex:

> I'm assuming the goal here is to build a low-noise source follower, with 
> the output buffered by an op amp.

No, a very low noise amplifier with 60 dB gain, 100 mHz to 1 MHz.
I'm aiming for 100pV/rtHz at least on the sweet spot.

> It looks like the non-inverting input of U1A is tied to a virtual 
> ground, and the inverting input is tied to the collector of Q3, I'm 
> guessing to try to use negative feedback to fix the collector voltage at 
> 4.57. But since Q3 is fed by current source Q2, the collector of Q3 
> (test point P3) is a high-impedance node and so it seems to me that the > only way the DC voltage there can be controlled is by U1A sensing the
> source voltage of the FET, through the R17/R23 network, and then around 
> the loop through the integrator (not shown) back to the gate of the FET, 
> if I'm understanding the circuit correctly.

The current source defines the bias current and the FET's gate voltage
is adjusted by an integrator until the cascode collector equals the
level of CENTER.


> The gain from the gate of the cascoded FET to the output of U1A isn't 
> well-defined; from "its perspective" it looks like a current source 
> loaded common-emitter amplifier feeding a transimpedance converter. It 
> will be very large. Plus the phase shift from U1A and the integrator to 
> the gate it sounds like a recipe for oscillation.

The signal gain from the gate to the output of U1A is determined by
the  gm of the FET array, which _is_ large and by the transimpedance
amplifier. (assuming open loop)

The current source and the cascode transistor do not enter the
equation other than second order effects like the ccs diverting
some signal current or that the BJT has probably a much higher
Early voltage and thus higher output impedance.

The integrator is also not in the signal path. It is as slow
as molasse. It takes a minute until the window comparator
thinks that the operating point has been reached. There may
be some influence in the mHz region, but I have no problem there.

> If I were dead-set on using a current source for the cascode collector 
> load I think it would be better to let one op-amp section handle a 
> feedback loop around the upper current source to set the DC bias at Q3's 
> collector, and let U1A and the integrator just handle setting the FET's 
> bias and the 0V DC level to the post amplifier. Delegate some 
> responsibility...

The current source is necessary to suppress the noise on VCC; without it
it takes a supply better than 2nV/rtHz (for 8 FETs and twice the
current). There also must be 5 diodes in series or the noise of
the current source emitter resistor starts playing a role.

Gerhard

who got a 54754A differential TDR plug in this morning, still a month
under service. That needs to be played with now.  :-)  :-)

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#462162

Gerhard Hoffmann wrote...
>
> Some observations:
>
>- Zin is negative also with the feedback loop cut

 I think you could safely add a little resistance
 in Q3's emitter.  BTW, while studying the Zin
 scene, you can make changes that would damage
 the noise performance, just saying.


-- 
 Thanks,
    - Win

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#462165

On 05/29/2017 10:36 AM, Winfield Hill wrote:
> Gerhard Hoffmann wrote...
>>
>> Some observations:
>>
>> - Zin is negative also with the feedback loop cut
> 
>   I think you could safely add a little resistance
>   in Q3's emitter.  BTW, while studying the Zin
>   scene, you can make changes that would damage
>   the noise performance, just saying.
> 
> 

If you have a chance could you confirm and/or deny that there might be a 
problem with the feedback connection from Q3's collector to U1A? It 
looks that way to me or else I'm not understanding correctly how this 
circuit is supposed to work, which is entirely possible given it's still 
before noon ;-)

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#462169

On a sunny day (Mon, 29 May 2017 11:20:44 -0400) it happened bitrex
<bitrex@de.lete.earthlink.net> wrote in <g%WWA.109122$Qg.95262@fx14.iad>:

>On 05/29/2017 10:36 AM, Winfield Hill wrote:
>> Gerhard Hoffmann wrote...
>>>
>>> Some observations:
>>>
>>> - Zin is negative also with the feedback loop cut
>> 
>>   I think you could safely add a little resistance
>>   in Q3's emitter.  BTW, while studying the Zin
>>   scene, you can make changes that would damage
>>   the noise performance, just saying.
>> 
>> 
>
>If you have a chance could you confirm and/or deny that there might be a 
>problem with the feedback connection from Q3's collector to U1A? It 
>looks that way to me or else I'm not understanding correctly how this 
>circuit is supposed to work, which is entirely possible given it's still 
>before noon ;-)

I looked at it twice and declined to comment as I 
1) have no idea what it does.
2) have no idea what it is supposed to do.
3) have no idea why make a peeseebee for something that one has not tested.
4) looks overly complicatiaotiantiated to me, brain abort.

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#462171

On 05/29/2017 11:36 AM, Jan Panteltje wrote:

> I looked at it twice and declined to comment as I
> 1) have no idea what it does.
> 2) have no idea what it is supposed to do.
> 3) have no idea why make a peeseebee for something that one has not tested.
> 4) looks overly complicatiaotiantiated to me, brain abort.
> 

Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.

I know I'm guilty of this myself sometimes, but while people are very 
familiar with their own designs I don't think everyone else can 
immediately intuit what's going on in a circuit that has say, more than 
a couple transistors or op amps. A few sentences of explanation of 
what's _supposed_ to happen would help OP a lot before jumping right 
into what the problems are with...whatever it is.

My impression was that it's a cascode source follower with U1A acting as 
a post amplifier, then feeding an integrator which then feeds the FET 
gate resistor. Holding the collector of the top cascode transistor at 
virtual ground by tying it to the op amp inverting input is clever, but 
it also seems sketchy as the only way U1A has to hold it there is around 
the loop to the FET gate. Transimpedance amp-connected op amp -> 
integrator is at least 270 degrees of phase shift at high frequency 
right off the bat. Seems sketch.

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