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[PATCH 0/4] Altera Partial Reconfiguration IP

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  [PATCH 0/4] Altera Partial Reconfiguration IP matthew.gerlach@linux.intel.com - 2017-02-15 22:20 +0100
    [PATCH 1/4] fpga: add config complete timeout matthew.gerlach@linux.intel.com - 2017-02-15 22:20 +0100
    [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-02-15 22:20 +0100
      Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial  Reconfiguration IP. Moritz Fischer <moritz.fischer@ettus.com> - 2017-02-16 18:40 +0100
        Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial  Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-02-16 23:50 +0100
    [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP. matthew.gerlach@linux.intel.com - 2017-02-15 22:20 +0100
      Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP. Dinh Nguyen <dinh.linux@gmail.com> - 2017-02-17 14:40 +0100
        Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP. Moritz Fischer <mdf@kernel.org> - 2017-02-17 16:30 +0100
      Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion  IP. Rob Herring <robh@kernel.org> - 2017-02-27 15:40 +0100
        Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion  IP. matthew.gerlach@linux.intel.com - 2017-02-27 17:40 +0100

#1581669 — [PATCH 0/4] Altera Partial Reconfiguration IP

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

This set of patches implements a fpga-mgr driver for the Altera Partial 
Reconfiguration IP.  The driver depends on a patch from Alan Tull that
adds a config complete timeout.  The driver code itself is divided into
core functions and functions to implement a platform driver. It is 
expected that drivers for other buses like PCIe would also use the core
functions.

Alan Tull (1):
  fpga: add config complete timeout

Matthew Gerlach (3):
  fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.
  fpga dt: bindings for Altera Partial Reconfiguraion IP.
  fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

 .../devicetree/bindings/fpga/altera-pr-ip.txt      |  12 ++
 drivers/fpga/Kconfig                               |  12 ++
 drivers/fpga/Makefile                              |   2 +
 drivers/fpga/altera-pr-ip-core-plat.c              |  65 ++++++
 drivers/fpga/altera-pr-ip-core.c                   | 217 +++++++++++++++++++++
 drivers/fpga/altera-pr-ip-core.h                   |  29 +++
 drivers/fpga/fpga-region.c                         |   3 +
 include/linux/fpga/fpga-mgr.h                      |   3 +
 8 files changed, 343 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

-- 
2.7.4

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#1581670 — [PATCH 1/4] fpga: add config complete timeout

From: Alan Tull <atull@opensource.altera.com>

Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
---
 drivers/fpga/fpga-region.c    | 3 +++
 include/linux/fpga/fpga-mgr.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
index 3222fdb..28401cb 100644
--- a/drivers/fpga/fpga-region.c
+++ b/drivers/fpga/fpga-region.c
@@ -381,6 +381,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
 	of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
 			     &info->disable_timeout_us);
 
+	of_property_read_u32(nd->overlay, "config-complete-timeout-us",
+			     &info->config_complete_timeout_us);
+
 	/* If FPGA was externally programmed, don't specify firmware */
 	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
 		pr_err("error: specified firmware and external-fpga-config");
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 57beb5d..fd3f083 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -76,11 +76,14 @@ enum fpga_mgr_states {
  * @flags: boolean flags as defined above
  * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
+ *	   status in the write_complete op.
  */
 struct fpga_image_info {
 	u32 flags;
 	u32 enable_timeout_us;
 	u32 disable_timeout_us;
+	u32 config_complete_timeout_us;
 };
 
 /**
-- 
2.7.4

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#1581671 — [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 drivers/fpga/Kconfig             |   5 +
 drivers/fpga/Makefile            |   1 +
 drivers/fpga/altera-pr-ip-core.c | 217 +++++++++++++++++++++++++++++++++++++++
 drivers/fpga/altera-pr-ip-core.h |  29 ++++++
 4 files changed, 252 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2..a46c173 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
 	  isolate one region of the FPGA from the busses while that
 	  region is being reprogrammed.
 
+config ALTERA_PR_IP_CORE
+        tristate "Altera Partial Reconfiguration IP Core"
+        help
+          Core driver support for Altera Partial Reconfiguration IP component
+
 endif # FPGA
 
 endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bc..82693d2 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
new file mode 100644
index 0000000..6ef60f3
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.c
@@ -0,0 +1,217 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull@opensource.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "altera-pr-ip-core.h"
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/module.h>
+
+#define ALT_PR_DATA_OFST		0x00
+#define ALT_PR_CSR_OFST			0x04
+
+#define ALT_PR_CSR_PR_START		BIT(0)
+#define ALT_PR_CSR_STATUS_SFT		2
+#define ALT_PR_CSR_STATUS_MSK		(7 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_NRESET	(0 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_ERR	(1 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_CRC_ERR	(2 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_BAD_BITS	(3 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_IN_PROG	(4 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_SUCCESS	(5 << ALT_PR_CSR_STATUS_SFT)
+
+struct alt_pr_priv {
+	void __iomem *reg_base;
+};
+
+static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	const char *err = "unknown";
+	enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
+	u32 val;
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	val &= ALT_PR_CSR_STATUS_MSK;
+
+	switch (val) {
+	case ALT_PR_CSR_STATUS_NRESET:
+		return FPGA_MGR_STATE_RESET;
+
+	case ALT_PR_CSR_STATUS_PR_ERR:
+		err = "pr error";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_CRC_ERR:
+		err = "crc error";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_BAD_BITS:
+		err = "bad bits";
+		ret = FPGA_MGR_STATE_WRITE_ERR;
+		break;
+
+	case ALT_PR_CSR_STATUS_PR_IN_PROG:
+		return FPGA_MGR_STATE_WRITE;
+
+	case ALT_PR_CSR_STATUS_PR_SUCCESS:
+		return FPGA_MGR_STATE_OPERATING;
+
+	default:
+		break;
+	}
+
+	dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
+		val, err, __func__);
+	return ret;
+}
+
+static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
+				  struct fpga_image_info *info,
+				  const char *buf, size_t count)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	u32 val;
+
+	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+		pr_err("%s Partial Reconfiguration flag not set\n", __func__);
+		return -EINVAL;
+	}
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	if (val & ALT_PR_CSR_PR_START) {
+		pr_err("%s Partial Reconfiguration already started\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
+
+	return 0;
+}
+
+static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
+			     size_t count)
+{
+	struct alt_pr_priv *priv = mgr->priv;
+	u32 *buffer_32 = (u32 *)buf;
+	size_t i = 0;
+
+	if (count <= 0)
+		return -EINVAL;
+
+	/* Write out the complete 32-bit chunks */
+	while (count >= sizeof(u32)) {
+		writel(buffer_32[i++], priv->reg_base);
+		count -= sizeof(u32);
+	}
+
+	/* Write out remaining non 32-bit chunks */
+	switch (count) {
+	case 3:
+		writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
+		break;
+	case 2:
+		writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
+		break;
+	case 1:
+		writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
+		break;
+	case 0:
+		break;
+	default:
+		/* This will never happen */
+		return -EFAULT;
+	}
+
+	if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
+		return -EIO;
+
+	return 0;
+}
+
+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
+				      struct fpga_image_info *info)
+{
+	u32 i;
+
+	for (i = 0; i < info->config_complete_timeout_us; i++) {
+		switch (alt_pr_fpga_state(mgr)) {
+		case FPGA_MGR_STATE_WRITE_ERR:
+			return -EIO;
+
+		case FPGA_MGR_STATE_OPERATING:
+			dev_info(&mgr->dev,
+				 "successful partial reconfiguration\n");
+			return 0;
+
+		default:
+			break;
+		}
+		udelay(1);
+	}
+	dev_err(&mgr->dev, "timed out waiting for write to complete\n");
+	return -ETIMEDOUT;
+}
+
+static const struct fpga_manager_ops alt_pr_ops = {
+	.state = alt_pr_fpga_state,
+	.write_init = alt_pr_fpga_write_init,
+	.write = alt_pr_fpga_write,
+	.write_complete = alt_pr_fpga_write_complete,
+};
+
+int alt_pr_probe(struct device *dev, void __iomem *reg_base)
+{
+	struct alt_pr_priv *priv;
+	u32 val;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->reg_base = reg_base;
+
+	val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+	dev_dbg(dev, "%s status=%d start=%d\n", __func__,
+		(val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
+		(int)(val & ALT_PR_CSR_PR_START));
+
+	return fpga_mgr_register(dev, dev_name(dev), &alt_pr_ops, priv);
+}
+EXPORT_SYMBOL_GPL(alt_pr_probe);
+
+int alt_pr_remove(struct device *dev)
+{
+	dev_dbg(dev, "%s\n", __func__);
+
+	fpga_mgr_unregister(dev);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(alt_pr_remove);
+
+MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach@linux.intel.com>");
+MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
new file mode 100644
index 0000000..cb73929
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.h
@@ -0,0 +1,29 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <atull@opensource.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ALT_PR_IP_CORE_H
+#define _ALT_PR_IP_CORE_H
+#include <linux/io.h>
+
+int alt_pr_probe(struct device *dev, void __iomem *reg_base);
+int alt_pr_remove(struct device *dev);
+
+#endif /* _ALT_PR_IP_CORE_H */
-- 
2.7.4

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#1582729 — Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

Hi Matthew,

On Wed, Feb 15, 2017 at 1:10 PM,  <matthew.gerlach@linux.intel.com> wrote:

> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info)
> +{
> +       u32 i;
> +
> +       for (i = 0; i < info->config_complete_timeout_us; i++) {
> +               switch (alt_pr_fpga_state(mgr)) {
> +               case FPGA_MGR_STATE_WRITE_ERR:
> +                       return -EIO;
> +
> +               case FPGA_MGR_STATE_OPERATING:
> +                       dev_info(&mgr->dev,
> +                                "successful partial reconfiguration\n");
> +                       return 0;
> +
> +               default:
> +                       break;
> +               }
> +               udelay(1);

Does this need to be a udelay? would a usleep_range() do maybe?

Could we maybe pull the timeout part into the framework if all drivers are doing
is to wait / poll for the state to be a certain value?

Thanks,

Moritz

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#1582984 — Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

Hi Moritz,

Thanks for the feedback.

On Thu, 16 Feb 2017, Moritz Fischer wrote:

> Hi Matthew,
>
> On Wed, Feb 15, 2017 at 1:10 PM,  <matthew.gerlach@linux.intel.com> wrote:
>
>> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
>> +                                     struct fpga_image_info *info)
>> +{
>> +       u32 i;
>> +
>> +       for (i = 0; i < info->config_complete_timeout_us; i++) {
>> +               switch (alt_pr_fpga_state(mgr)) {
>> +               case FPGA_MGR_STATE_WRITE_ERR:
>> +                       return -EIO;
>> +
>> +               case FPGA_MGR_STATE_OPERATING:
>> +                       dev_info(&mgr->dev,
>> +                                "successful partial reconfiguration\n");
>> +                       return 0;
>> +
>> +               default:
>> +                       break;
>> +               }
>> +               udelay(1);
>
> Does this need to be a udelay? would a usleep_range() do maybe?

The actual timeout required is design specific.  The member,
config_complete_timeout_us, is defined in microseconds, and my experience 
is that a small number of microseconds (e.g. < 10) is usually plenty. 
Other FPGAs and designs might be different.  My quick reading of kernel 
timers says usleep_range() is good for 10 us - 20 ms.  In this driver, if 
usleep_range(1) can put less pressure on the CPU and schedular at the cost 
of little accuracy, I will be happy to switch, but at this time I don't 
know if usleep_range() would be better or not.


>
> Could we maybe pull the timeout part into the framework if all drivers are doing
> is to wait / poll for the state to be a certain value?
>

I think it is safe to say that all variations of FPGAs need some amount of 
time after the bitstream to be delivered before the FPGA is "ready".  If 
that time is exceeded then the fpga programming has failed.  If all FPGA 
variations are doing a poll for some amount of time, then it would be good 
to move the polling up to the framework.  I think such a change would be 
better in its own patch set.

> Thanks,
>
> Moritz
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fpga" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

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#1581673 — [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Device Tree bindings for Altera Partial Reconfiguraion IP?

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
new file mode 100644
index 0000000..ada821f
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
@@ -0,0 +1,12 @@
+Altera Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,pr-ip"
+- reg        : base address and size for memory mapped io.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ff20c000 {
+		compatible = "altr,pr-ip";
+		reg = <0xff20c000 0x10>;
+	};
-- 
2.7.4

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#1583413 — Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

On Wed, Feb 15, 2017 at 3:10 PM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Device Tree bindings for Altera Partial Reconfiguraion IP?
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>

Nit: your commit header s/Reconfiguraion/Reconfiguration

Dinh

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#1583525 — Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

Matthew,

On Fri, Feb 17, 2017 at 5:31 AM, Dinh Nguyen <dinh.linux@gmail.com> wrote:
> On Wed, Feb 15, 2017 at 3:10 PM,  <matthew.gerlach@linux.intel.com> wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Device Tree bindings for Altera Partial Reconfiguraion IP?
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-By: Moritz Fischer <mdf@kernel.org>
>> ---
>>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>>
>
> Nit: your commit header s/Reconfiguraion/Reconfiguration
>
> Dinh

Thanks,
Moritz

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#1588682 — Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

On Wed, Feb 15, 2017 at 01:10:37PM -0800, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Device Tree bindings for Altera Partial Reconfiguraion IP?
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> 
> diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> new file mode 100644
> index 0000000..ada821f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> @@ -0,0 +1,12 @@
> +Altera Partial Reconfiguration IP
> +
> +Required properties:
> +- compatible : should contain "altr,pr-ip"

Kind of generic. There's only one version of h/w?

> +- reg        : base address and size for memory mapped io.
> +
> +Example:
> +
> +	fpga_mgr: fpga-mgr@ff20c000 {
> +		compatible = "altr,pr-ip";
> +		reg = <0xff20c000 0x10>;
> +	};
> -- 
> 2.7.4
> 

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#1588802 — Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

On Mon, 27 Feb 2017, Rob Herring wrote:

Hi Rob,


> On Wed, Feb 15, 2017 at 01:10:37PM -0800, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Device Tree bindings for Altera Partial Reconfiguraion IP?
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>>
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>> new file mode 100644
>> index 0000000..ada821f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>> @@ -0,0 +1,12 @@
>> +Altera Partial Reconfiguration IP
>> +
>> +Required properties:
>> +- compatible : should contain "altr,pr-ip"
>
> Kind of generic. There's only one version of h/w?


Fair point on being generic.  It does match the published documentation, 
but we could be more specific with "altr,a10-pr-ip" because it 
really is only for an Arria10.

Matthew Gerlach

>
>> +- reg        : base address and size for memory mapped io.
>> +
>> +Example:
>> +
>> +	fpga_mgr: fpga-mgr@ff20c000 {
>> +		compatible = "altr,pr-ip";
>> +		reg = <0xff20c000 0x10>;
>> +	};
>> --
>> 2.7.4
>>
>

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