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Groups > linux.kernel > #1663565 > unrolled thread

[PATCH 00/12] coresight: Support for ARM Coresight SoC-600

Started bySuzuki K Poulose <suzuki.poulose@arm.com>
First post2017-06-12 16:40 +0200
Last post2017-06-15 12:30 +0200
Articles 20 on this page of 24 — 4 participants

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  [PATCH 00/12] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
    [PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
      Re: [PATCH 04/12] coresight: Add support for reading 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-13 19:50 +0200
        Re: [PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-13 20:00 +0200
    [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
      Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit  registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 19:50 +0200
        Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit  registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:20 +0200
          Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mike Leach <mike.leach@linaro.org> - 2017-06-15 15:40 +0200
          Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:30 +0200
    [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
      Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
        Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:20 +0200
    [PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
    [PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
      Re: [PATCH 09/12] coresight tmc: Add capability information Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:30 +0200
        Re: [PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:40 +0200
          Re: [PATCH 09/12] coresight tmc: Add capability information Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:40 +0200
    [PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
      Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
        Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:30 +0200
          Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:40 +0200
    [PATCH 07/12] coresight replicator: Expose replicator management registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:50 +0200
      Re: [PATCH 07/12] coresight replicator: Expose replicator management  registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
        Re: [PATCH 07/12] coresight replicator: Expose replicator management  registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:30 +0200

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#1663565 — [PATCH 00/12] coresight: Support for ARM Coresight SoC-600

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 00/12] coresight: Support for ARM Coresight SoC-600
Message-ID<tRyFz-3h6-3@gated-at.bofh.it>
This series adds support for ARM Coresight SoC-600 IP, which implements
Coresight V3 architecture. It also does some clean up of the replicator
driver namings used in the driver to prevent confusions to the user.

The SoC-600 comes with an improved TMC which supports new features,
including Save-Restore and Software FIFO2 mode (for streaming the trace
data over functional I/O like USB/PCI).
This series only supports Save-Restore feature of the new ETR by reusing
the driver to perform additional setups required in case we are dealing
with an IP which supports it. Towards this, we add a capability
description to the IP listings to make it easier.

Patches 1-8 contains general cleanups, introduction of some helper
routines.
Patch 9 introduces the capability tracking for TMCs.
Patch 10 adds the support for Save-Restore feature in ETR.
Patch 11 adds support for the Coresight SoC 600 TMC
Patch 12 adds the support for other components in SoC 600.

Tested on Juno (with Coresight SoC 400) and an FPGA based system
for SoC 600.

Suzuki K Poulose (12):
  coresight replicator: Cleanup programmable replicator naming
  arm64: dts: juno: Use the new coresight replicator string
  coresight: Extend the PIDR mask to cover relevant bits in PIDR2
  coresight: Add support for reading 64bit registers
  coresight tmc: Add helpers for accessing 64bit registers
  coresight tmc: Expose DBA and AXICTL
  coresight replicator: Expose replicator management registers
  coresight tmc: Handle configuration types properly
  coresight tmc: Add capability information
  coresight tmc: Support for save-restore in ETR
  coresight tmc: Add support for Coresight SoC 600 TMC
  coresight: Add support for Coresight SoC 600 components

 .../devicetree/bindings/arm/coresight.txt          |  4 +-
 arch/arm64/boot/dts/arm/juno-base.dtsi             |  2 +-
 drivers/hwtracing/coresight/Kconfig                | 10 ++--
 drivers/hwtracing/coresight/Makefile               |  2 +-
 drivers/hwtracing/coresight/coresight-funnel.c     |  9 +++-
 drivers/hwtracing/coresight/coresight-priv.h       | 35 +++++++++++--
 .../coresight/coresight-replicator-qcom.c          | 33 ++++++++++--
 drivers/hwtracing/coresight/coresight-stm.c        |  8 +--
 drivers/hwtracing/coresight/coresight-tmc-etf.c    |  8 +--
 drivers/hwtracing/coresight/coresight-tmc-etr.c    | 21 ++++++--
 drivers/hwtracing/coresight/coresight-tmc.c        | 58 ++++++++++++++++++----
 drivers/hwtracing/coresight/coresight-tmc.h        | 53 ++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-tpiu.c       |  9 +++-
 13 files changed, 210 insertions(+), 42 deletions(-)

-- 
2.7.4

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#1663567 — [PATCH 04/12] coresight: Add support for reading 64bit registers

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 04/12] coresight: Add support for reading 64bit registers
Message-ID<tRyFA-3h6-25@gated-at.bofh.it>
In reply to#1663565
Add support for reading a lower and upper 32bits of a register
as a single 64bit register.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-priv.h | 27 ++++++++++++++++++++++-----
 drivers/hwtracing/coresight/coresight-tmc.c  |  6 +++---
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 5f662d8..b62dc6a 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -39,23 +39,29 @@
 #define ETM_MODE_EXCL_USER	BIT(31)
 
 typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
-#define coresight_simple_func(type, func, name, offset)			\
+#define __coresight_simple_func(type, func, name, lo_off, hi_off)	\
 static ssize_t name##_show(struct device *_dev,				\
 			   struct device_attribute *attr, char *buf)	\
 {									\
 	type *drvdata = dev_get_drvdata(_dev->parent);			\
 	coresight_read_fn fn = func;					\
-	u32 val;							\
+	u64 val;							\
 	pm_runtime_get_sync(_dev->parent);				\
 	if (fn)								\
-		val = fn(_dev->parent, offset);				\
+		val = (u64)fn(_dev->parent, lo_off);			\
 	else								\
-		val = readl_relaxed(drvdata->base + offset);		\
+		val = coresight_read_reg_pair(drvdata->base,		\
+						 lo_off, hi_off);	\
 	pm_runtime_put_sync(_dev->parent);				\
-	return scnprintf(buf, PAGE_SIZE, "0x%x\n", val);		\
+	return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val);		\
 }									\
 static DEVICE_ATTR_RO(name)
 
+#define coresight_simple_func(type, func, name, offset)			\
+	__coresight_simple_func(type, func, name, offset, -1)
+#define coresight_simple_reg64(type, name, lo_off, hi_off)		\
+	__coresight_simple_func(type, NULL, name, lo_off, hi_off)
+
 enum etm_addr_type {
 	ETM_ADDR_TYPE_NONE,
 	ETM_ADDR_TYPE_SINGLE,
@@ -106,6 +112,17 @@ static inline void CS_UNLOCK(void __iomem *addr)
 	} while (0);
 }
 
+static inline u64
+coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
+{
+	u64 val;
+
+	val = readl_relaxed(addr + lo_offset);
+	val |= (hi_offset < 0) ? 0 :
+		(u64)readl_relaxed(addr + hi_offset) << 32;
+	return val;
+}
+
 void coresight_disable_path(struct list_head *path);
 int coresight_enable_path(struct list_head *path, u32 mode);
 struct coresight_device *coresight_get_sink(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index eb0c7b3..7025982 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -219,11 +219,8 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
 
 #define coresight_tmc_simple_func(name, offset)			\
 	coresight_simple_func(struct tmc_drvdata, NULL, name, offset)
-
 coresight_tmc_simple_func(rsz, TMC_RSZ);
 coresight_tmc_simple_func(sts, TMC_STS);
-coresight_tmc_simple_func(rrp, TMC_RRP);
-coresight_tmc_simple_func(rwp, TMC_RWP);
 coresight_tmc_simple_func(trg, TMC_TRG);
 coresight_tmc_simple_func(ctl, TMC_CTL);
 coresight_tmc_simple_func(ffsr, TMC_FFSR);
@@ -232,6 +229,9 @@ coresight_tmc_simple_func(mode, TMC_MODE);
 coresight_tmc_simple_func(pscr, TMC_PSCR);
 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
 
+coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
+coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
+
 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 	&dev_attr_rsz.attr,
 	&dev_attr_sts.attr,
-- 
2.7.4

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#1665056 — Re: [PATCH 04/12] coresight: Add support for reading 64bit registers

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-13 19:50 +0200
SubjectRe: [PATCH 04/12] coresight: Add support for reading 64bit registers
Message-ID<tRY6Z-2tP-9@gated-at.bofh.it>
In reply to#1663567
On Mon, Jun 12, 2017 at 03:36:43PM +0100, Suzuki K Poulose wrote:
> Add support for reading a lower and upper 32bits of a register
> as a single 64bit register.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Just a few cosmetic details...

> ---
>  drivers/hwtracing/coresight/coresight-priv.h | 27 ++++++++++++++++++++++-----
>  drivers/hwtracing/coresight/coresight-tmc.c  |  6 +++---
>  2 files changed, 25 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index 5f662d8..b62dc6a 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -39,23 +39,29 @@
>  #define ETM_MODE_EXCL_USER	BIT(31)
>  
>  typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
> -#define coresight_simple_func(type, func, name, offset)			\
> +#define __coresight_simple_func(type, func, name, lo_off, hi_off)	\
>  static ssize_t name##_show(struct device *_dev,				\
>  			   struct device_attribute *attr, char *buf)	\
>  {									\
>  	type *drvdata = dev_get_drvdata(_dev->parent);			\
>  	coresight_read_fn fn = func;					\
> -	u32 val;							\
> +	u64 val;							\
>  	pm_runtime_get_sync(_dev->parent);				\
>  	if (fn)								\
> -		val = fn(_dev->parent, offset);				\
> +		val = (u64)fn(_dev->parent, lo_off);			\
>  	else								\
> -		val = readl_relaxed(drvdata->base + offset);		\
> +		val = coresight_read_reg_pair(drvdata->base,		\
> +						 lo_off, hi_off);	\
>  	pm_runtime_put_sync(_dev->parent);				\
> -	return scnprintf(buf, PAGE_SIZE, "0x%x\n", val);		\
> +	return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val);		\
>  }									\
>  static DEVICE_ATTR_RO(name)
>  
> +#define coresight_simple_func(type, func, name, offset)			\
> +	__coresight_simple_func(type, func, name, offset, -1)
> +#define coresight_simple_reg64(type, name, lo_off, hi_off)		\
> +	__coresight_simple_func(type, NULL, name, lo_off, hi_off)
> +
>  enum etm_addr_type {
>  	ETM_ADDR_TYPE_NONE,
>  	ETM_ADDR_TYPE_SINGLE,
> @@ -106,6 +112,17 @@ static inline void CS_UNLOCK(void __iomem *addr)
>  	} while (0);
>  }
>  
> +static inline u64
> +coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
> +{
> +	u64 val;
> +
> +	val = readl_relaxed(addr + lo_offset);
> +	val |= (hi_offset < 0) ? 0 :
> +		(u64)readl_relaxed(addr + hi_offset) << 32;

This should probably be aligned with the other '('.

> +	return val;
> +}
> +
>  void coresight_disable_path(struct list_head *path);
>  int coresight_enable_path(struct list_head *path, u32 mode);
>  struct coresight_device *coresight_get_sink(struct list_head *path);
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index eb0c7b3..7025982 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -219,11 +219,8 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
>  
>  #define coresight_tmc_simple_func(name, offset)			\
>  	coresight_simple_func(struct tmc_drvdata, NULL, name, offset)
> -

Please restore.

>  coresight_tmc_simple_func(rsz, TMC_RSZ);
>  coresight_tmc_simple_func(sts, TMC_STS);
> -coresight_tmc_simple_func(rrp, TMC_RRP);
> -coresight_tmc_simple_func(rwp, TMC_RWP);
>  coresight_tmc_simple_func(trg, TMC_TRG);
>  coresight_tmc_simple_func(ctl, TMC_CTL);
>  coresight_tmc_simple_func(ffsr, TMC_FFSR);
> @@ -232,6 +229,9 @@ coresight_tmc_simple_func(mode, TMC_MODE);
>  coresight_tmc_simple_func(pscr, TMC_PSCR);
>  coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
>  

No need for a new line here.  In fact I would put the following two lines in
place of the ones you've replaced above.

> +coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
> +coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
> +
>  static struct attribute *coresight_tmc_mgmt_attrs[] = {
>  	&dev_attr_rsz.attr,
>  	&dev_attr_sts.attr,
> -- 
> 2.7.4
>

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#1665070 — Re: [PATCH 04/12] coresight: Add support for reading 64bit registers

FromSuzuki K Poulose <Suzuki.Poulose@arm.com>
Date2017-06-13 20:00 +0200
SubjectRe: [PATCH 04/12] coresight: Add support for reading 64bit registers
Message-ID<tRYgG-2x8-9@gated-at.bofh.it>
In reply to#1665056
On 13/06/17 18:45, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:43PM +0100, Suzuki K Poulose wrote:
>> Add support for reading a lower and upper 32bits of a register
>> as a single 64bit register.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> Just a few cosmetic details...

Will fix all of them in the next version.

Thanks for the review.

Suzuki

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#1663568 — [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers
Message-ID<tRyFA-3h6-27@gated-at.bofh.it>
In reply to#1663565
Coresight TMC splits 64bit registers into a pair of 32bit registers
(e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-priv.h    |  8 ++++++++
 drivers/hwtracing/coresight/coresight-tmc-etf.c |  8 ++++----
 drivers/hwtracing/coresight/coresight-tmc-etr.c |  8 ++++----
 drivers/hwtracing/coresight/coresight-tmc.h     | 19 +++++++++++++++++++
 4 files changed, 35 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index b62dc6a..1a16964 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -123,6 +123,14 @@ coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
 	return val;
 }
 
+static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
+						 s32 lo_offset, s32 hi_offset)
+{
+	writel_relaxed((u32)val, addr + lo_offset);
+	if (hi_offset >= 0)
+		writel_relaxed((u32)(val >> 32), addr + hi_offset);
+}
+
 void coresight_disable_path(struct list_head *path);
 int coresight_enable_path(struct list_head *path, u32 mode);
 struct coresight_device *coresight_get_sink(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index e3b9fb8..aecd712 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -371,7 +371,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
 {
 	int i, cur;
 	u32 *buf_ptr;
-	u32 read_ptr, write_ptr;
+	u64 read_ptr, write_ptr;
 	u32 status, to_read;
 	unsigned long offset;
 	struct cs_buffers *buf = sink_config;
@@ -388,8 +388,8 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
 
 	tmc_flush_and_stop(drvdata);
 
-	read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
-	write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
+	read_ptr = tmc_read_rrp(drvdata);
+	write_ptr = tmc_read_rwp(drvdata);
 
 	/*
 	 * Get a hold of the status register and see if a wrap around
@@ -441,7 +441,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
 		if (read_ptr > (drvdata->size - 1))
 			read_ptr -= drvdata->size;
 		/* Tell the HW */
-		writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
+		tmc_write_rrp(drvdata, read_ptr);
 		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
 	}
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 5d31269..ff11b92 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -44,9 +44,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
 		  TMC_AXICTL_PROT_CTL_B1;
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
+	tmc_write_dba(drvdata, drvdata->paddr);
 
-	writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
-	writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
 	writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 		       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
 		       TMC_FFCR_TRIGON_TRIGIN,
@@ -59,9 +58,10 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 
 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
 {
-	u32 rwp, val;
+	u64 rwp;
+	u32 val;
 
-	rwp = readl_relaxed(drvdata->base + TMC_RWP);
+	rwp = tmc_read_rwp(drvdata);
 	val = readl_relaxed(drvdata->base + TMC_STS);
 
 	/*
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 51c0185..c78de00 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -18,6 +18,7 @@
 #ifndef _CORESIGHT_TMC_H
 #define _CORESIGHT_TMC_H
 
+#include <linux/io.h>
 #include <linux/miscdevice.h>
 
 #define TMC_RSZ			0x004
@@ -139,4 +140,22 @@ extern const struct coresight_ops tmc_etf_cs_ops;
 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
 extern const struct coresight_ops tmc_etr_cs_ops;
+
+
+#define TMC_REG_PAIR(name, lo_off, hi_off)				\
+static inline u64							\
+tmc_read_##name(struct tmc_drvdata *drvdata)				\
+{									\
+	return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);	\
+}									\
+static inline void							\
+tmc_write_##name(struct tmc_drvdata *drvdata, u64 val)			\
+{									\
+	coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);	\
+}
+
+TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
+TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
+TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
+
 #endif
-- 
2.7.4

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#1666113 — Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-14 19:50 +0200
SubjectRe: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers
Message-ID<tSkAx-8cx-15@gated-at.bofh.it>
In reply to#1663568
On Mon, Jun 12, 2017 at 03:36:44PM +0100, Suzuki K Poulose wrote:
> Coresight TMC splits 64bit registers into a pair of 32bit registers
> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.

I'm good with this patch but please specify these changes are to support the
SoC-600 suite.  That way when we look back at this set in a couple of years we
don't loose hair thinking we've been carrying bugs all this time.

> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-priv.h    |  8 ++++++++
>  drivers/hwtracing/coresight/coresight-tmc-etf.c |  8 ++++----
>  drivers/hwtracing/coresight/coresight-tmc-etr.c |  8 ++++----
>  drivers/hwtracing/coresight/coresight-tmc.h     | 19 +++++++++++++++++++
>  4 files changed, 35 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index b62dc6a..1a16964 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -123,6 +123,14 @@ coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
>  	return val;
>  }
>  
> +static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
> +						 s32 lo_offset, s32 hi_offset)
> +{
> +	writel_relaxed((u32)val, addr + lo_offset);
> +	if (hi_offset >= 0)
> +		writel_relaxed((u32)(val >> 32), addr + hi_offset);
> +}
> +
>  void coresight_disable_path(struct list_head *path);
>  int coresight_enable_path(struct list_head *path, u32 mode);
>  struct coresight_device *coresight_get_sink(struct list_head *path);
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index e3b9fb8..aecd712 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -371,7 +371,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
>  {
>  	int i, cur;
>  	u32 *buf_ptr;
> -	u32 read_ptr, write_ptr;
> +	u64 read_ptr, write_ptr;
>  	u32 status, to_read;
>  	unsigned long offset;
>  	struct cs_buffers *buf = sink_config;
> @@ -388,8 +388,8 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
>  
>  	tmc_flush_and_stop(drvdata);
>  
> -	read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
> -	write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
> +	read_ptr = tmc_read_rrp(drvdata);
> +	write_ptr = tmc_read_rwp(drvdata);
>  
>  	/*
>  	 * Get a hold of the status register and see if a wrap around
> @@ -441,7 +441,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
>  		if (read_ptr > (drvdata->size - 1))
>  			read_ptr -= drvdata->size;
>  		/* Tell the HW */
> -		writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
> +		tmc_write_rrp(drvdata, read_ptr);
>  		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>  	}
>  
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 5d31269..ff11b92 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -44,9 +44,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
>  		  ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
>  		  TMC_AXICTL_PROT_CTL_B1;
>  	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
> +	tmc_write_dba(drvdata, drvdata->paddr);
>  
> -	writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
> -	writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
>  	writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
>  		       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
>  		       TMC_FFCR_TRIGON_TRIGIN,
> @@ -59,9 +58,10 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
>  
>  static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
>  {
> -	u32 rwp, val;
> +	u64 rwp;
> +	u32 val;
>  
> -	rwp = readl_relaxed(drvdata->base + TMC_RWP);
> +	rwp = tmc_read_rwp(drvdata);
>  	val = readl_relaxed(drvdata->base + TMC_STS);
>  
>  	/*
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 51c0185..c78de00 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -18,6 +18,7 @@
>  #ifndef _CORESIGHT_TMC_H
>  #define _CORESIGHT_TMC_H
>  
> +#include <linux/io.h>
>  #include <linux/miscdevice.h>
>  
>  #define TMC_RSZ			0x004
> @@ -139,4 +140,22 @@ extern const struct coresight_ops tmc_etf_cs_ops;
>  int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
>  int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
>  extern const struct coresight_ops tmc_etr_cs_ops;
> +
> +
> +#define TMC_REG_PAIR(name, lo_off, hi_off)				\
> +static inline u64							\
> +tmc_read_##name(struct tmc_drvdata *drvdata)				\
> +{									\
> +	return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);	\
> +}									\
> +static inline void							\
> +tmc_write_##name(struct tmc_drvdata *drvdata, u64 val)			\
> +{									\
> +	coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);	\
> +}
> +
> +TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
> +TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
> +TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
> +
>  #endif
> -- 
> 2.7.4
>

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#1666623 — Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers

FromSuzuki K Poulose <Suzuki.Poulose@arm.com>
Date2017-06-15 12:20 +0200
SubjectRe: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers
Message-ID<tSA2B-1bK-5@gated-at.bofh.it>
In reply to#1666113
On 14/06/17 18:49, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:44PM +0100, Suzuki K Poulose wrote:
>> Coresight TMC splits 64bit registers into a pair of 32bit registers
>> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
>
> I'm good with this patch but please specify these changes are to support the
> SoC-600 suite.  That way when we look back at this set in a couple of years we
> don't loose hair thinking we've been carrying bugs all this time.

To be honest, these are not necessarily just for the support of SoC-600.
It is applies to the current driver with SoC-400, as you could see below,
where we have always assumed that the RRP/RWP/DBA HI bits are always
0. Technically, the TMC supports upto 40bits and hence we have been doing
it wrong.

>> -	read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
>> -	write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
>> +	read_ptr = tmc_read_rrp(drvdata);
>> +	write_ptr = tmc_read_rwp(drvdata);



>> -		writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
>> +		tmc_write_rrp(drvdata, read_ptr);
>>  		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);

>>  	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>> +	tmc_write_dba(drvdata, drvdata->paddr);
>>
>> -	writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
>> -	writel_relaxed(0x0, drvdata->base + TMC_DBAHI);

>>
>> -	rwp = readl_relaxed(drvdata->base + TMC_RWP);
>> +	rwp = tmc_read_rwp(drvdata);
>>  	val = readl_relaxed(drvdata->base + TMC_STS);
>>


Suzuki

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#1666724 — Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers

FromMike Leach <mike.leach@linaro.org>
Date2017-06-15 15:40 +0200
SubjectRe: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers
Message-ID<tSDa9-33m-5@gated-at.bofh.it>
In reply to#1666623
Part of the perf / ETR SG work I have been doing use the HI bits -
which makes these additions useful for that too.
I'd be aiming to use these as part of the re-spin
Mike

On 15 June 2017 at 11:13, Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
> On 14/06/17 18:49, Mathieu Poirier wrote:
>>
>> On Mon, Jun 12, 2017 at 03:36:44PM +0100, Suzuki K Poulose wrote:
>>>
>>> Coresight TMC splits 64bit registers into a pair of 32bit registers
>>> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
>>
>>
>> I'm good with this patch but please specify these changes are to support
>> the
>> SoC-600 suite.  That way when we look back at this set in a couple of
>> years we
>> don't loose hair thinking we've been carrying bugs all this time.
>
>
> To be honest, these are not necessarily just for the support of SoC-600.
> It is applies to the current driver with SoC-400, as you could see below,
> where we have always assumed that the RRP/RWP/DBA HI bits are always
> 0. Technically, the TMC supports upto 40bits and hence we have been doing
> it wrong.
>
>>> -       read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
>>> -       write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
>>> +       read_ptr = tmc_read_rrp(drvdata);
>>> +       write_ptr = tmc_read_rwp(drvdata);
>
>
>
>
>>> -               writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
>>> +               tmc_write_rrp(drvdata, read_ptr);
>>>                 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>
>
>>>         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>>> +       tmc_write_dba(drvdata, drvdata->paddr);
>>>
>>> -       writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
>>> -       writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
>
>
>>>
>>> -       rwp = readl_relaxed(drvdata->base + TMC_RWP);
>>> +       rwp = tmc_read_rwp(drvdata);
>>>         val = readl_relaxed(drvdata->base + TMC_STS);
>>>
>
>
> Suzuki
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Blackburn Design Centre. UK

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#1666758 — Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-15 16:30 +0200
SubjectRe: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers
Message-ID<tSDWy-3yH-15@gated-at.bofh.it>
In reply to#1666623
On 15 June 2017 at 04:13, Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
> On 14/06/17 18:49, Mathieu Poirier wrote:
>>
>> On Mon, Jun 12, 2017 at 03:36:44PM +0100, Suzuki K Poulose wrote:
>>>
>>> Coresight TMC splits 64bit registers into a pair of 32bit registers
>>> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
>>
>>
>> I'm good with this patch but please specify these changes are to support
>> the
>> SoC-600 suite.  That way when we look back at this set in a couple of
>> years we
>> don't loose hair thinking we've been carrying bugs all this time.
>
>
> To be honest, these are not necessarily just for the support of SoC-600.
> It is applies to the current driver with SoC-400, as you could see below,
> where we have always assumed that the RRP/RWP/DBA HI bits are always
> 0. Technically, the TMC supports upto 40bits and hence we have been doing
> it wrong.

I just had another look at the documentation and you are correct -
disregard my comment for this patch.

>
>>> -       read_ptr = readl_relaxed(drvdata->base + TMC_RRP);
>>> -       write_ptr = readl_relaxed(drvdata->base + TMC_RWP);
>>> +       read_ptr = tmc_read_rrp(drvdata);
>>> +       write_ptr = tmc_read_rwp(drvdata);
>
>
>
>
>>> -               writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
>>> +               tmc_write_rrp(drvdata, read_ptr);
>>>                 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>
>
>>>         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
>>> +       tmc_write_dba(drvdata, drvdata->paddr);
>>>
>>> -       writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
>>> -       writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
>
>
>>>
>>> -       rwp = readl_relaxed(drvdata->base + TMC_RWP);
>>> +       rwp = tmc_read_rwp(drvdata);
>>>         val = readl_relaxed(drvdata->base + TMC_STS);
>>>
>
>
> Suzuki

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#1663570 — [PATCH 06/12] coresight tmc: Expose DBA and AXICTL

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 06/12] coresight tmc: Expose DBA and AXICTL
Message-ID<tRyFA-3h6-29@gated-at.bofh.it>
In reply to#1663565
Expose DBALO,DBAHI and AXICTL registers

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 7025982..fd5a2e0 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -228,9 +228,11 @@ coresight_tmc_simple_func(ffcr, TMC_FFCR);
 coresight_tmc_simple_func(mode, TMC_MODE);
 coresight_tmc_simple_func(pscr, TMC_PSCR);
 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
+coresight_tmc_simple_func(axictl, TMC_AXICTL);
 
 coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
 coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
+coresight_simple_reg64(struct tmc_drvdata, dba, TMC_DBALO, TMC_DBAHI);
 
 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 	&dev_attr_rsz.attr,
@@ -244,6 +246,8 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
 	&dev_attr_mode.attr,
 	&dev_attr_pscr.attr,
 	&dev_attr_devid.attr,
+	&dev_attr_dba.attr,
+	&dev_attr_axictl.attr,
 	NULL,
 };
 
-- 
2.7.4

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#1666117 — Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-14 20:00 +0200
SubjectRe: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL
Message-ID<tSkKd-8fL-9@gated-at.bofh.it>
In reply to#1663570
On Mon, Jun 12, 2017 at 03:36:45PM +0100, Suzuki K Poulose wrote:
> Expose DBALO,DBAHI and AXICTL registers

Why is this needed?  I fear we are exposing internal kernel information.

> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index 7025982..fd5a2e0 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -228,9 +228,11 @@ coresight_tmc_simple_func(ffcr, TMC_FFCR);
>  coresight_tmc_simple_func(mode, TMC_MODE);
>  coresight_tmc_simple_func(pscr, TMC_PSCR);
>  coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
> +coresight_tmc_simple_func(axictl, TMC_AXICTL);
>  
>  coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
>  coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
> +coresight_simple_reg64(struct tmc_drvdata, dba, TMC_DBALO, TMC_DBAHI);
>  
>  static struct attribute *coresight_tmc_mgmt_attrs[] = {
>  	&dev_attr_rsz.attr,
> @@ -244,6 +246,8 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
>  	&dev_attr_mode.attr,
>  	&dev_attr_pscr.attr,
>  	&dev_attr_devid.attr,
> +	&dev_attr_dba.attr,
> +	&dev_attr_axictl.attr,
>  	NULL,
>  };
>  
> -- 
> 2.7.4
>

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#1666622 — Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL

FromSuzuki K Poulose <Suzuki.Poulose@arm.com>
Date2017-06-15 12:20 +0200
SubjectRe: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL
Message-ID<tSA2B-1bK-3@gated-at.bofh.it>
In reply to#1666117
On 14/06/17 18:50, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:45PM +0100, Suzuki K Poulose wrote:
>> Expose DBALO,DBAHI and AXICTL registers
>
> Why is this needed?  I fear we are exposing internal kernel information.
>

Mathieu,

These are useful to analyse/debug the trace session. e.g, we could compare
RRP/RWP with DBA to see if the trace is actually generated or not.
As such, we already expose RRP/RWP. Exposing DBA doesn't expose
more information than we do already. Also, when we add SG support
this will be useful, as DBA will never match (or be in the range of) RRP/RWP.

The AXICTL may not be of any significance right now, but will be
useful once we add scatter gather support, to check which mode
are we operating in.

Let me know if you still have concerns.

Suzuki

>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>>  drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
>> index 7025982..fd5a2e0 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
>> @@ -228,9 +228,11 @@ coresight_tmc_simple_func(ffcr, TMC_FFCR);
>>  coresight_tmc_simple_func(mode, TMC_MODE);
>>  coresight_tmc_simple_func(pscr, TMC_PSCR);
>>  coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
>> +coresight_tmc_simple_func(axictl, TMC_AXICTL);
>>
>>  coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
>>  coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
>> +coresight_simple_reg64(struct tmc_drvdata, dba, TMC_DBALO, TMC_DBAHI);
>>
>>  static struct attribute *coresight_tmc_mgmt_attrs[] = {
>>  	&dev_attr_rsz.attr,
>> @@ -244,6 +246,8 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
>>  	&dev_attr_mode.attr,
>>  	&dev_attr_pscr.attr,
>>  	&dev_attr_devid.attr,
>> +	&dev_attr_dba.attr,
>> +	&dev_attr_axictl.attr,
>>  	NULL,
>>  };
>>
>> --
>> 2.7.4
>>

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#1663571 — [PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string
Message-ID<tRyFB-3h6-35@gated-at.bofh.it>
In reply to#1663565
Use the new compatible for ATB programmable replicator in Juno.

Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index bfe7d68..c82c706 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -373,7 +373,7 @@
 	};
 
 	replicator@20120000 {
-		compatible = "qcom,coresight-replicator1x", "arm,primecell";
+		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 		reg = <0 0x20120000 0 0x1000>;
 
 		clocks = <&soc_smc50mhz>;
-- 
2.7.4

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#1663575 — [PATCH 09/12] coresight tmc: Add capability information

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 09/12] coresight tmc: Add capability information
Message-ID<tRyFB-3h6-41@gated-at.bofh.it>
In reply to#1663565
This patch adds description of the capabilities of a given TMC.
This will help us to handle different versions of the TMC in the
same driver by checking the capabilities.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 10 +++++++++-
 drivers/hwtracing/coresight/coresight-tmc.h | 18 ++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 7152656..e88f2f3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -399,16 +399,24 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 	ret = misc_register(&drvdata->miscdev);
 	if (ret)
 		coresight_unregister(drvdata->csdev);
+	else if (id->data)
+		drvdata->caps = *(struct tmc_caps *)id->data;
 out:
 	return ret;
 }
 
+static struct tmc_caps coresight_soc_400_tmc_caps = {
+	.caps = CORESIGHT_SOC_400_TMC_CAPS,
+};
+
 static struct amba_id tmc_ids[] = {
 	{
+		/* Coresight SoC 400 TMC */
 		.id     = 0x000bb961,
 		.mask   = 0x000fffff,
+		.data	= &coresight_soc_400_tmc_caps,
 	},
-	{ 0, 0},
+	{},
 };
 
 static struct amba_driver tmc_driver = {
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index c78de00..87e4561 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -89,6 +89,18 @@ enum tmc_mem_intf_width {
 	TMC_MEM_INTF_WIDTH_256BITS	= 8,
 };
 
+#define TMC_CAP_ETR_SG_UNIT			(1U << 0)
+
+/**
+ * struct tmc_cap - Describes the capabilities of the TMC.
+ * @caps:	- Bitmask of the capacities
+ */
+struct tmc_caps {
+	u32	caps;
+};
+
+#define CORESIGHT_SOC_400_TMC_CAPS	(TMC_CAP_ETR_SG_UNIT)
+
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
  * @base:	memory mapped base address for this component.
@@ -110,6 +122,7 @@ struct tmc_drvdata {
 	void __iomem		*base;
 	struct device		*dev;
 	struct coresight_device	*csdev;
+	struct tmc_caps		caps;
 	struct miscdevice	miscdev;
 	spinlock_t		spinlock;
 	bool			reading;
@@ -158,4 +171,9 @@ TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
 
+static inline bool tmc_has_cap(struct tmc_drvdata *drvdata, u32 cap)
+{
+	return !!(drvdata->caps.caps & cap);
+}
+
 #endif
-- 
2.7.4

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#1666135 — Re: [PATCH 09/12] coresight tmc: Add capability information

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-14 20:30 +0200
SubjectRe: [PATCH 09/12] coresight tmc: Add capability information
Message-ID<tSldg-cr-5@gated-at.bofh.it>
In reply to#1663575
On Mon, Jun 12, 2017 at 03:36:48PM +0100, Suzuki K Poulose wrote:
> This patch adds description of the capabilities of a given TMC.
> This will help us to handle different versions of the TMC in the
> same driver by checking the capabilities.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 10 +++++++++-
>  drivers/hwtracing/coresight/coresight-tmc.h | 18 ++++++++++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index 7152656..e88f2f3 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -399,16 +399,24 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>  	ret = misc_register(&drvdata->miscdev);
>  	if (ret)
>  		coresight_unregister(drvdata->csdev);
> +	else if (id->data)
> +		drvdata->caps = *(struct tmc_caps *)id->data;
>  out:
>  	return ret;
>  }
>  
> +static struct tmc_caps coresight_soc_400_tmc_caps = {
> +	.caps = CORESIGHT_SOC_400_TMC_CAPS,
> +};
> +
>  static struct amba_id tmc_ids[] = {
>  	{
> +		/* Coresight SoC 400 TMC */
>  		.id     = 0x000bb961,
>  		.mask   = 0x000fffff,
> +		.data	= &coresight_soc_400_tmc_caps,

Do we need this?  I don't see anywhere a check for TMC_CAP_ETR_SG_UNIT.  And
I also suppose that the SoC600 suite also supports scatter-gather - is there a
need to differenciate both that may not be implemented in this set?

I'm also wondering if capabilities for SoC600 could not be retrieved from HW
registers rather than hard coded?

>  	},
> -	{ 0, 0},
> +	{},
>  };
>  
>  static struct amba_driver tmc_driver = {
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index c78de00..87e4561 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -89,6 +89,18 @@ enum tmc_mem_intf_width {
>  	TMC_MEM_INTF_WIDTH_256BITS	= 8,
>  };
>  
> +#define TMC_CAP_ETR_SG_UNIT			(1U << 0)
> +
> +/**
> + * struct tmc_cap - Describes the capabilities of the TMC.
> + * @caps:	- Bitmask of the capacities
> + */
> +struct tmc_caps {
> +	u32	caps;
> +};
> +
> +#define CORESIGHT_SOC_400_TMC_CAPS	(TMC_CAP_ETR_SG_UNIT)
> +
>  /**
>   * struct tmc_drvdata - specifics associated to an TMC component
>   * @base:	memory mapped base address for this component.
> @@ -110,6 +122,7 @@ struct tmc_drvdata {
>  	void __iomem		*base;
>  	struct device		*dev;
>  	struct coresight_device	*csdev;
> +	struct tmc_caps		caps;

A simple u32 is probably best here rather than introducing a new structure.  If
capabilites can't be retrieved from HW and have to be declared statically, a
*u32 referencing ->data is sufficient rather than copying memory.

>  	struct miscdevice	miscdev;
>  	spinlock_t		spinlock;
>  	bool			reading;
> @@ -158,4 +171,9 @@ TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
>  TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
>  TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
>  
> +static inline bool tmc_has_cap(struct tmc_drvdata *drvdata, u32 cap)
> +{
> +	return !!(drvdata->caps.caps & cap);
> +}
> +
>  #endif
> -- 
> 2.7.4
>

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#1666627 — Re: [PATCH 09/12] coresight tmc: Add capability information

FromSuzuki K Poulose <Suzuki.Poulose@arm.com>
Date2017-06-15 12:40 +0200
SubjectRe: [PATCH 09/12] coresight tmc: Add capability information
Message-ID<tSAlX-1jO-1@gated-at.bofh.it>
In reply to#1666135
On 14/06/17 19:22, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:48PM +0100, Suzuki K Poulose wrote:
>> This patch adds description of the capabilities of a given TMC.
>> This will help us to handle different versions of the TMC in the
>> same driver by checking the capabilities.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>>  drivers/hwtracing/coresight/coresight-tmc.c | 10 +++++++++-
>>  drivers/hwtracing/coresight/coresight-tmc.h | 18 ++++++++++++++++++
>>  2 files changed, 27 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
>> index 7152656..e88f2f3 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
>> @@ -399,16 +399,24 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>>  	ret = misc_register(&drvdata->miscdev);
>>  	if (ret)
>>  		coresight_unregister(drvdata->csdev);
>> +	else if (id->data)
>> +		drvdata->caps = *(struct tmc_caps *)id->data;
>>  out:
>>  	return ret;
>>  }
>>
>> +static struct tmc_caps coresight_soc_400_tmc_caps = {
>> +	.caps = CORESIGHT_SOC_400_TMC_CAPS,
>> +};
>> +
>>  static struct amba_id tmc_ids[] = {
>>  	{
>> +		/* Coresight SoC 400 TMC */
>>  		.id     = 0x000bb961,
>>  		.mask   = 0x000fffff,
>> +		.data	= &coresight_soc_400_tmc_caps,
>
> Do we need this?  I don't see anywhere a check for TMC_CAP_ETR_SG_UNIT.  And
> I also suppose that the SoC600 suite also supports scatter-gather - is there a
> need to differenciate both that may not be implemented in this set?

Yes, the coresight SoC-600 doesn't come with an in built Scatter Gather unit.
Instead there is a dedicated component (Coresight Address Translation UNIT, CATU)
to do the Scatter Gather, which needs a driver. This is to make sure that if
somebody wants to use the SG, they should check it in the caps.


>
> I'm also wondering if capabilities for SoC600 could not be retrieved from HW
> registers rather than hard coded?

Unfortunately, no. There is no hardware description for the feature. So, we need
to depend on the PIDs to detect the features.

>> +#define TMC_CAP_ETR_SG_UNIT			(1U << 0)
>> +
>> +/**
>> + * struct tmc_cap - Describes the capabilities of the TMC.
>> + * @caps:	- Bitmask of the capacities
>> + */
>> +struct tmc_caps {
>> +	u32	caps;
>> +};
>> +
>> +#define CORESIGHT_SOC_400_TMC_CAPS	(TMC_CAP_ETR_SG_UNIT)
>> +
>>  /**
>>   * struct tmc_drvdata - specifics associated to an TMC component
>>   * @base:	memory mapped base address for this component.
>> @@ -110,6 +122,7 @@ struct tmc_drvdata {
>>  	void __iomem		*base;
>>  	struct device		*dev;
>>  	struct coresight_device	*csdev;
>> +	struct tmc_caps		caps;
>
> A simple u32 is probably best here rather than introducing a new structure.  If
> capabilites can't be retrieved from HW and have to be declared statically, a
> *u32 referencing ->data is sufficient rather than copying memory.

I think eventually the compiler may be able to do a register move to copy a 32bit
data. We could potentially add more fields there (e.g, whether a CATU is connected
to the device or not etc). Hence the abstraction.


Suzuki

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#1666765 — Re: [PATCH 09/12] coresight tmc: Add capability information

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-15 16:40 +0200
SubjectRe: [PATCH 09/12] coresight tmc: Add capability information
Message-ID<tSE6e-3E5-23@gated-at.bofh.it>
In reply to#1666627
On 15 June 2017 at 04:30, Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
> On 14/06/17 19:22, Mathieu Poirier wrote:
>>
>> On Mon, Jun 12, 2017 at 03:36:48PM +0100, Suzuki K Poulose wrote:
>>>
>>> This patch adds description of the capabilities of a given TMC.
>>> This will help us to handle different versions of the TMC in the
>>> same driver by checking the capabilities.
>>>
>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> ---
>>>  drivers/hwtracing/coresight/coresight-tmc.c | 10 +++++++++-
>>>  drivers/hwtracing/coresight/coresight-tmc.h | 18 ++++++++++++++++++
>>>  2 files changed, 27 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c
>>> b/drivers/hwtracing/coresight/coresight-tmc.c
>>> index 7152656..e88f2f3 100644
>>> --- a/drivers/hwtracing/coresight/coresight-tmc.c
>>> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
>>> @@ -399,16 +399,24 @@ static int tmc_probe(struct amba_device *adev,
>>> const struct amba_id *id)
>>>         ret = misc_register(&drvdata->miscdev);
>>>         if (ret)
>>>                 coresight_unregister(drvdata->csdev);
>>> +       else if (id->data)
>>> +               drvdata->caps = *(struct tmc_caps *)id->data;
>>>  out:
>>>         return ret;
>>>  }
>>>
>>> +static struct tmc_caps coresight_soc_400_tmc_caps = {
>>> +       .caps = CORESIGHT_SOC_400_TMC_CAPS,
>>> +};
>>> +
>>>  static struct amba_id tmc_ids[] = {
>>>         {
>>> +               /* Coresight SoC 400 TMC */
>>>                 .id     = 0x000bb961,
>>>                 .mask   = 0x000fffff,
>>> +               .data   = &coresight_soc_400_tmc_caps,
>>
>>
>> Do we need this?  I don't see anywhere a check for TMC_CAP_ETR_SG_UNIT.
>> And
>> I also suppose that the SoC600 suite also supports scatter-gather - is
>> there a
>> need to differenciate both that may not be implemented in this set?
>
>
> Yes, the coresight SoC-600 doesn't come with an in built Scatter Gather
> unit.
> Instead there is a dedicated component (Coresight Address Translation UNIT,
> CATU)
> to do the Scatter Gather, which needs a driver. This is to make sure that if
> somebody wants to use the SG, they should check it in the caps.
>
>
>>
>> I'm also wondering if capabilities for SoC600 could not be retrieved from
>> HW
>> registers rather than hard coded?
>
>
> Unfortunately, no. There is no hardware description for the feature. So, we
> need
> to depend on the PIDs to detect the features.

I suspected that much - thanks for the clarification.

>
>>> +#define TMC_CAP_ETR_SG_UNIT                    (1U << 0)
>>> +
>>> +/**
>>> + * struct tmc_cap - Describes the capabilities of the TMC.
>>> + * @caps:      - Bitmask of the capacities
>>> + */
>>> +struct tmc_caps {
>>> +       u32     caps;
>>> +};
>>> +
>>> +#define CORESIGHT_SOC_400_TMC_CAPS     (TMC_CAP_ETR_SG_UNIT)
>>> +
>>>  /**
>>>   * struct tmc_drvdata - specifics associated to an TMC component
>>>   * @base:      memory mapped base address for this component.
>>> @@ -110,6 +122,7 @@ struct tmc_drvdata {
>>>         void __iomem            *base;
>>>         struct device           *dev;
>>>         struct coresight_device *csdev;
>>> +       struct tmc_caps         caps;
>>
>>
>> A simple u32 is probably best here rather than introducing a new
>> structure.  If
>> capabilites can't be retrieved from HW and have to be declared statically,
>> a
>> *u32 referencing ->data is sufficient rather than copying memory.
>
>
> I think eventually the compiler may be able to do a register move to copy a
> 32bit
> data. We could potentially add more fields there (e.g, whether a CATU is
> connected
> to the device or not etc). Hence the abstraction.

Ok

>
>
> Suzuki

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#1663577 — [PATCH 08/12] coresight tmc: Handle configuration types properly

FromSuzuki K Poulose <suzuki.poulose@arm.com>
Date2017-06-12 16:40 +0200
Subject[PATCH 08/12] coresight tmc: Handle configuration types properly
Message-ID<tRyFB-3h6-43@gated-at.bofh.it>
In reply to#1663565
Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. Make sure
the driver handles the new type properly.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index fd5a2e0..7152656 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -358,11 +358,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 	desc.dev = dev;
 	desc.groups = coresight_tmc_groups;
 
-	if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
+	switch (drvdata->config_type) {
+	case TMC_CONFIG_TYPE_ETB:
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etb_cs_ops;
-	} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
+		break;
+	case TMC_CONFIG_TYPE_ETR:
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etr_cs_ops;
@@ -373,10 +375,16 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 		if (ret)
 			goto out;
-	} else {
+		break;
+	case TMC_CONFIG_TYPE_ETF:
 		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 		desc.ops = &tmc_etf_cs_ops;
+		break;
+	default:
+		pr_err("%s: Unsupported TMC config\n", pdata->name);
+		ret = -EINVAL;
+		goto out;
 	}
 
 	drvdata->csdev = coresight_register(&desc);
-- 
2.7.4

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#1666115 — Re: [PATCH 08/12] coresight tmc: Handle configuration types properly

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-06-14 20:00 +0200
SubjectRe: [PATCH 08/12] coresight tmc: Handle configuration types properly
Message-ID<tSkKd-8fL-5@gated-at.bofh.it>
In reply to#1663577
On Mon, Jun 12, 2017 at 03:36:47PM +0100, Suzuki K Poulose wrote:
> Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
> Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. Make sure
> the driver handles the new type properly.

From what I see below this patch only improves readability by moving the if/else
compound to a case statement - there is no trace of the new ETS block.
Readability enhancement are good but the changelog must match the code.
 
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index fd5a2e0..7152656 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -358,11 +358,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>  	desc.dev = dev;
>  	desc.groups = coresight_tmc_groups;
>  
> -	if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
> +	switch (drvdata->config_type) {
> +	case TMC_CONFIG_TYPE_ETB:
>  		desc.type = CORESIGHT_DEV_TYPE_SINK;
>  		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>  		desc.ops = &tmc_etb_cs_ops;
> -	} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
> +		break;
> +	case TMC_CONFIG_TYPE_ETR:
>  		desc.type = CORESIGHT_DEV_TYPE_SINK;
>  		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>  		desc.ops = &tmc_etr_cs_ops;
> @@ -373,10 +375,16 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>  		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
>  		if (ret)
>  			goto out;
> -	} else {
> +		break;
> +	case TMC_CONFIG_TYPE_ETF:
>  		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
>  		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
>  		desc.ops = &tmc_etf_cs_ops;
> +		break;
> +	default:
> +		pr_err("%s: Unsupported TMC config\n", pdata->name);
> +		ret = -EINVAL;
> +		goto out;
>  	}
>  
>  	drvdata->csdev = coresight_register(&desc);
> -- 
> 2.7.4
>

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#1666625 — Re: [PATCH 08/12] coresight tmc: Handle configuration types properly

FromSuzuki K Poulose <Suzuki.Poulose@arm.com>
Date2017-06-15 12:30 +0200
SubjectRe: [PATCH 08/12] coresight tmc: Handle configuration types properly
Message-ID<tSAci-1ga-7@gated-at.bofh.it>
In reply to#1666115
On 14/06/17 18:59, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:47PM +0100, Suzuki K Poulose wrote:
>> Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
>> Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. Make sure
>> the driver handles the new type properly.
>
> From what I see below this patch only improves readability by moving the if/else
> compound to a case statement - there is no trace of the new ETS block.
> Readability enhancement are good but the changelog must match the code.

Mathieu,

Not really. It fixes an issue with the current code. We check for ETB and ETR,
if it doesn't match either of those, we assume it is ETF which is fine with SoC-400.
But with SoC-600, we could have an ETS with id 0x3 and the driver could treat it
as an ETF and go on with the initialisation. This patch makes sure that we
do check for the ETF and report that ETS is not a supported configuration.

Suzuki

>
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>>  drivers/hwtracing/coresight/coresight-tmc.c | 14 +++++++++++---
>>  1 file changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
>> index fd5a2e0..7152656 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
>> @@ -358,11 +358,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>>  	desc.dev = dev;
>>  	desc.groups = coresight_tmc_groups;
>>
>> -	if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
>> +	switch (drvdata->config_type) {
>> +	case TMC_CONFIG_TYPE_ETB:
>>  		desc.type = CORESIGHT_DEV_TYPE_SINK;
>>  		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>>  		desc.ops = &tmc_etb_cs_ops;
>> -	} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
>> +		break;
>> +	case TMC_CONFIG_TYPE_ETR:
>>  		desc.type = CORESIGHT_DEV_TYPE_SINK;
>>  		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>>  		desc.ops = &tmc_etr_cs_ops;
>> @@ -373,10 +375,16 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
>>  		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
>>  		if (ret)
>>  			goto out;
>> -	} else {
>> +		break;
>> +	case TMC_CONFIG_TYPE_ETF:
>>  		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
>>  		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
>>  		desc.ops = &tmc_etf_cs_ops;
>> +		break;
>> +	default:
>> +		pr_err("%s: Unsupported TMC config\n", pdata->name);
>> +		ret = -EINVAL;
>> +		goto out;
>>  	}
>>
>>  	drvdata->csdev = coresight_register(&desc);
>> --
>> 2.7.4
>>

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