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Groups > linux.kernel > #1666622
| From | Suzuki K Poulose <Suzuki.Poulose@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL |
| Date | 2017-06-15 12:20 +0200 |
| Message-ID | <tSA2B-1bK-3@gated-at.bofh.it> (permalink) |
| References | <tRyFz-3h6-3@gated-at.bofh.it> <tRyFA-3h6-29@gated-at.bofh.it> <tSkKd-8fL-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 14/06/17 18:50, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:45PM +0100, Suzuki K Poulose wrote:
>> Expose DBALO,DBAHI and AXICTL registers
>
> Why is this needed? I fear we are exposing internal kernel information.
>
Mathieu,
These are useful to analyse/debug the trace session. e.g, we could compare
RRP/RWP with DBA to see if the trace is actually generated or not.
As such, we already expose RRP/RWP. Exposing DBA doesn't expose
more information than we do already. Also, when we add SG support
this will be useful, as DBA will never match (or be in the range of) RRP/RWP.
The AXICTL may not be of any significance right now, but will be
useful once we add scatter gather support, to check which mode
are we operating in.
Let me know if you still have concerns.
Suzuki
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
>> index 7025982..fd5a2e0 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
>> @@ -228,9 +228,11 @@ coresight_tmc_simple_func(ffcr, TMC_FFCR);
>> coresight_tmc_simple_func(mode, TMC_MODE);
>> coresight_tmc_simple_func(pscr, TMC_PSCR);
>> coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
>> +coresight_tmc_simple_func(axictl, TMC_AXICTL);
>>
>> coresight_simple_reg64(struct tmc_drvdata, rrp, TMC_RRP, TMC_RRPHI);
>> coresight_simple_reg64(struct tmc_drvdata, rwp, TMC_RWP, TMC_RWPHI);
>> +coresight_simple_reg64(struct tmc_drvdata, dba, TMC_DBALO, TMC_DBAHI);
>>
>> static struct attribute *coresight_tmc_mgmt_attrs[] = {
>> &dev_attr_rsz.attr,
>> @@ -244,6 +246,8 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
>> &dev_attr_mode.attr,
>> &dev_attr_pscr.attr,
>> &dev_attr_devid.attr,
>> + &dev_attr_dba.attr,
>> + &dev_attr_axictl.attr,
>> NULL,
>> };
>>
>> --
>> 2.7.4
>>
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[PATCH 00/12] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
[PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 04/12] coresight: Add support for reading 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-13 19:50 +0200
Re: [PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-13 20:00 +0200
[PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 19:50 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:20 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mike Leach <mike.leach@linaro.org> - 2017-06-15 15:40 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:30 +0200
[PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:20 +0200
[PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
[PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 09/12] coresight tmc: Add capability information Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:30 +0200
Re: [PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:40 +0200
Re: [PATCH 09/12] coresight tmc: Add capability information Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:40 +0200
[PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:30 +0200
Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:40 +0200
[PATCH 07/12] coresight replicator: Expose replicator management registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:50 +0200
Re: [PATCH 07/12] coresight replicator: Expose replicator management registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
Re: [PATCH 07/12] coresight replicator: Expose replicator management registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:30 +0200
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