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Groups > linux.kernel > #1653007 > unrolled thread
| Started by | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| First post | 2017-05-30 11:20 +0200 |
| Last post | 2017-05-30 16:20 +0200 |
| Articles | 6 — 2 participants |
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[PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - 2017-05-30 11:20 +0200
[PATCH 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - 2017-05-30 11:20 +0200
[PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - 2017-05-30 11:20 +0200
Re: [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K Marc Zyngier <marc.zyngier@arm.com> - 2017-05-30 16:10 +0200
Re: [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - 2017-05-30 16:30 +0200
Re: [PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K Marc Zyngier <marc.zyngier@arm.com> - 2017-05-30 16:20 +0200
| From | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| Date | 2017-05-30 11:20 +0200 |
| Subject | [PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K |
| Message-ID | <tMLtL-5qE-3@gated-at.bofh.it> |
Hello, The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which contains the CPU cores) and the CP (which contains most peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs, doubling the number of available peripherals. In terms of interrupt handling, all devices in the CPs are connected through wired interrupt to a unit called ICU located in each CP. This unit converts the wired interrupts from the devices into memory transactions. Inside the AP, there is a GIC extension called GICP, which allows a memory write transaction to trigger a GIC SPI interrupt. The ICUs in each CP are therefore configured to trigger a memory write into the appropriate GICP register so that a wired interrupt from a CP device is converted into a memory write, itself converted into a regular GIC SPI interrupt. Until now, the configuration of the ICU was done statically by the firmware, and therefore the Device Tree files in Linux were specifying directly GIC interrupts for the interrupts of CP devices. However, with the growing number of devices in the CP, a static allocation scheme doesn't work for the long term. This patch series therefore makes Linux aware of the ICU: GIC SPI interrupts are dynamically allocated, and the ICU is configured accordingly to route a CP wired interrupt to the allocated GIC SPI interrupt. In detail: - The first two patches are the Device Tree binding patches - The third patch is a minimal driver for the GICP unit. All it does is clear interrupts that may have been left pending by the firmware. - The fourth patch is the most important done, which adds the driver for the ICU itself. - The fifth patch adjust Kconfig.platforms to select the GICP and ICU drivers. - The last patch adjusts the Device Tree files of the Armada 7K/8K to use the ICU. Best regards, Thomas Thomas Petazzoni (6): dt-bindings: interrupt-controller: add DT binding for the Marvell GICP dt-bindings: interrupt-controller: add DT binding for the Marvell ICU irqchip: irq-mvebu-gicp: new driver for Marvell GICP irqchip: irq-mvebu-icu: new driver for Marvell ICU arm64: marvell: enable ICU and GICP drivers arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K .../bindings/interrupt-controller/marvell,gicp.txt | 20 ++ .../bindings/interrupt-controller/marvell,icu.txt | 57 ++++ arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 5 + .../boot/dts/marvell/armada-cp110-master.dtsi | 60 ++-- .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 54 +-- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-mvebu-gicp.c | 53 +++ drivers/irqchip/irq-mvebu-icu.c | 373 +++++++++++++++++++++ .../dt-bindings/interrupt-controller/mvebu-icu.h | 15 + 11 files changed, 599 insertions(+), 48 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt create mode 100644 drivers/irqchip/irq-mvebu-gicp.c create mode 100644 drivers/irqchip/irq-mvebu-icu.c create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h -- 2.7.4
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| From | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| Date | 2017-05-30 11:20 +0200 |
| Subject | [PATCH 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP |
| Message-ID | <tMLtN-5qE-51@gated-at.bofh.it> |
| In reply to | #1653007 |
This commit adds the Device Tree binding documentation for the Marvell
GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
using memory transactions. It is used by the ICU unit in the Marvell
CP110 block to turn wired interrupts inside the CP into SPI interrupts
at the GIC level in the AP.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
.../bindings/interrupt-controller/marvell,gicp.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
new file mode 100644
index 0000000..996bdbf
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
@@ -0,0 +1,20 @@
+Marvell GICP Controller
+-----------------------
+
+GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
+interrupts by doing a memory transaction. It is used by the ICU
+located in the Marvell CP110 to turn wired interrupts inside the CP
+into GIC SPI interrupts.
+
+Required properties:
+
+- compatible: Must be "marvell,gicp"
+
+- reg: Must be the address and size of the GICP SPI registers
+
+Example:
+
+gicp_spi: gicp-spi@3f0040 {
+ compatible = "marvell,gicp";
+ reg = <0x3f0040 0x10>;
+};
--
2.7.4
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| From | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| Date | 2017-05-30 11:20 +0200 |
| Subject | [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K |
| Message-ID | <tMLtN-5qE-49@gated-at.bofh.it> |
| In reply to | #1653007 |
This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
to describe the ICU and GICP units, and use ICU interrupts for all
devices in the CP110 blocks.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 5 ++
.../boot/dts/marvell/armada-cp110-master.dtsi | 60 +++++++++++++---------
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 54 ++++++++++---------
3 files changed, 71 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index fe41bf9..cb87831 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -146,6 +146,11 @@
marvell,spi-base = <128>, <136>, <144>, <152>;
};
+ gicp: gicp@3f0040 {
+ compatible = "marvell,gicp";
+ reg = <0x3f0040 0x10>;
+ };
+
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index ac8df52..fe899e8 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -44,19 +44,20 @@
* Device Tree file for Marvell Armada CP110 Master.
*/
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+
/ {
cp110-master {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&cpm_icu>;
ranges;
config-space@f2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_ethernet: ethernet@0 {
@@ -68,21 +69,21 @@
dma-coherent;
cpm_eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -96,6 +97,15 @@
reg = <0x12a200 0x10>;
};
+ cpm_icu: interrupt-controller@1e0000 {
+ compatible = "marvell,icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ gicp = <&gicp>;
+ };
+
cpm_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
@@ -120,14 +130,14 @@
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 15>;
status = "disabled";
};
@@ -137,7 +147,7 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 22>;
status = "disabled";
};
@@ -147,7 +157,7 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 23>;
status = "disabled";
};
@@ -195,7 +205,7 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
@@ -205,7 +215,7 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
@@ -213,7 +223,7 @@
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 25>;
status = "okay";
};
@@ -221,7 +231,7 @@
cpm_sdhci0: sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&cpm_syscon0 1 4>;
dma-coherent;
@@ -231,13 +241,13 @@
cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+ interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_syscon0 1 26>;
@@ -264,8 +274,8 @@
/* non-prefetchable memory */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
status = "disabled";
@@ -290,8 +300,8 @@
/* non-prefetchable memory */
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 11>;
@@ -317,8 +327,8 @@
/* non-prefetchable memory */
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 12>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 7740a75..f9cf4f3 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -49,14 +49,13 @@
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&cps_icu>;
ranges;
config-space@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_rtc: rtc@284000 {
@@ -75,21 +74,21 @@
dma-coherent;
cps_eth0: eth0 {
- interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -103,6 +102,15 @@
reg = <0x12a200 0x10>;
};
+ cps_icu: interrupt-controller@1e0000 {
+ compatible = "marvell,icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ gicp = <&gicp>;
+ };
+
cps_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
@@ -127,7 +135,7 @@
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 15>;
status = "disabled";
};
@@ -137,7 +145,7 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 22>;
status = "disabled";
};
@@ -147,7 +155,7 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 23>;
status = "disabled";
};
@@ -195,7 +203,7 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
@@ -205,7 +213,7 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
@@ -213,7 +221,7 @@
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 25>;
status = "okay";
};
@@ -221,13 +229,13 @@
cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+ interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_syscon0 1 26>;
@@ -254,8 +262,8 @@
/* non-prefetchable memory */
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 13>;
status = "disabled";
@@ -280,8 +288,8 @@
/* non-prefetchable memory */
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 11>;
@@ -307,8 +315,8 @@
/* non-prefetchable memory */
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 12>;
--
2.7.4
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2017-05-30 16:10 +0200 |
| Subject | Re: [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K |
| Message-ID | <tMQ0q-8oA-11@gated-at.bofh.it> |
| In reply to | #1653009 |
On 30/05/17 10:16, Thomas Petazzoni wrote:
> This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
> to describe the ICU and GICP units, and use ICU interrupts for all
> devices in the CP110 blocks.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 5 ++
> .../boot/dts/marvell/armada-cp110-master.dtsi | 60 +++++++++++++---------
> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 54 ++++++++++---------
> 3 files changed, 71 insertions(+), 48 deletions(-)
>
[...]
> @@ -221,13 +229,13 @@
> cps_crypto: crypto@800000 {
> compatible = "inside-secure,safexcel-eip197";
> reg = <0x800000 0x200000>;
> - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
> + interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
> | IRQ_TYPE_LEVEL_HIGH)>,
I've already mentioned this in a separate thread to Antoine, but it'd be
good to fix this non-sensical configuration.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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| From | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| Date | 2017-05-30 16:30 +0200 |
| Subject | Re: [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K |
| Message-ID | <tMQjM-8vK-11@gated-at.bofh.it> |
| In reply to | #1653261 |
Hello,
On Tue, 30 May 2017 15:02:34 +0100, Marc Zyngier wrote:
> > @@ -221,13 +229,13 @@
> > cps_crypto: crypto@800000 {
> > compatible = "inside-secure,safexcel-eip197";
> > reg = <0x800000 0x200000>;
> > - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
> > + interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
> > | IRQ_TYPE_LEVEL_HIGH)>,
>
> I've already mentioned this in a separate thread to Antoine, but it'd be
> good to fix this non-sensical configuration.
Antoine has already submitted a patch, and it has been merged by
Grégory already [1]. I simply didn't base my patches on top of the
latest patch from Antoine, but Grégory will handle the merge conflict
when applying the DT changes.
Thanks!
Thomas
[1] http://git.infradead.org/linux-mvebu.git/commitdiff/44f73dc42c11398d7b84e94365a485ebd6420798
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2017-05-30 16:20 +0200 |
| Message-ID | <tMQa5-8s0-5@gated-at.bofh.it> |
| In reply to | #1653007 |
Hi Thomas, On 30/05/17 10:16, Thomas Petazzoni wrote: > Hello, > > The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which > contains the CPU cores) and the CP (which contains most > peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs, > doubling the number of available peripherals. > > In terms of interrupt handling, all devices in the CPs are connected > through wired interrupt to a unit called ICU located in each CP. This > unit converts the wired interrupts from the devices into memory > transactions. > > Inside the AP, there is a GIC extension called GICP, which allows a > memory write transaction to trigger a GIC SPI interrupt. The ICUs in > each CP are therefore configured to trigger a memory write into the > appropriate GICP register so that a wired interrupt from a CP device > is converted into a memory write, itself converted into a regular GIC > SPI interrupt. > > Until now, the configuration of the ICU was done statically by the > firmware, and therefore the Device Tree files in Linux were specifying > directly GIC interrupts for the interrupts of CP devices. However, > with the growing number of devices in the CP, a static allocation > scheme doesn't work for the long term. > > This patch series therefore makes Linux aware of the ICU: GIC SPI > interrupts are dynamically allocated, and the ICU is configured > accordingly to route a CP wired interrupt to the allocated GIC SPI > interrupt. > > In detail: > > - The first two patches are the Device Tree binding patches > > - The third patch is a minimal driver for the GICP unit. All it does > is clear interrupts that may have been left pending by the > firmware. > > - The fourth patch is the most important done, which adds the driver > for the ICU itself. > > - The fifth patch adjust Kconfig.platforms to select the GICP and ICU > drivers. > > - The last patch adjusts the Device Tree files of the Armada 7K/8K to > use the ICU. For a first drop, this looks quite good, and the few comments I've had should be pretty easy to address. Looking forward to reviewing v2. Thanks, M. -- Jazz is not dead. It just smells funny...
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