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Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

Started byMark Rutland <mark.rutland@arm.com>
First post2017-04-27 18:50 +0200
Last post2017-05-05 01:40 +0200
Articles 6 — 4 participants

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  Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium  ThunderX2 erratum #74 Mark Rutland <mark.rutland@arm.com> - 2017-04-27 18:50 +0200
    Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium  ThunderX2 erratum #74 Will Deacon <will.deacon@arm.com> - 2017-04-27 19:10 +0200
      Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium  ThunderX2 erratum #74 Geetha Akula <geethasowjanya.akula@gmail.com> - 2017-05-02 08:40 +0200
        Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium  ThunderX2 erratum #74 Will Deacon <will.deacon@arm.com> - 2017-05-03 11:50 +0200
          Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium  ThunderX2 erratum #74 Geetha Akula <geethasowjanya.akula@gmail.com> - 2017-05-03 12:40 +0200
          Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium  ThunderX2 erratum #74 Jon Masters <jcm@jonmasters.org> - 2017-05-05 01:40 +0200

#1632256 — Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

FromMark Rutland <mark.rutland@arm.com>
Date2017-04-27 18:50 +0200
SubjectRe: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
Message-ID<tAUMa-3dZ-11@gated-at.bofh.it>
On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> +	/*
> +	 * Override the size, for Cavium CN99xx implementations
> +	 * which doesn't support the page 1 SMMU register space.
> +	 */
> +	cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> +	if (cpu_model == MIDR_THUNDERX_99XX ||
> +	    cpu_model == MIDR_BRCM_VULCAN)
> +		size = SZ_64K;

If you're trying to identify an SMMU erratum, identify the SMMU, not the
CPU it happens to be paired with this time.

There are ID registers in the SMMU you can use to do so.

NAK to using the CPU ID here.

Mark.

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#1632268

FromWill Deacon <will.deacon@arm.com>
Date2017-04-27 19:10 +0200
Message-ID<tAV5v-3A6-9@gated-at.bofh.it>
In reply to#1632256
On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> > +	/*
> > +	 * Override the size, for Cavium CN99xx implementations
> > +	 * which doesn't support the page 1 SMMU register space.
> > +	 */
> > +	cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> > +	if (cpu_model == MIDR_THUNDERX_99XX ||
> > +	    cpu_model == MIDR_BRCM_VULCAN)
> > +		size = SZ_64K;
> 
> If you're trying to identify an SMMU erratum, identify the SMMU, not the
> CPU it happens to be paired with this time.
> 
> There are ID registers in the SMMU you can use to do so.
> 
> NAK to using the CPU ID here.

Agreed. I had some off-list discussion with Geetha where we agreed to use
the "silicon ID", which I assumed was the SMMU IIDR register.

Will

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#1634167

FromGeetha Akula <geethasowjanya.akula@gmail.com>
Date2017-05-02 08:40 +0200
Message-ID<tCzDz-2Il-1@gated-at.bofh.it>
In reply to#1632268
Hi Will,

SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
If using MIDR is not accepted, can we enable errata based on SMMU resource size?
some thing like below.

static bool page0_reg_only = false;
+static unsigned long arm_smmu_resource_size(void)
+{
+       if (page0_reg_only)
+               return SZ_64K;
+       else
+               return SZ_128K;
+}
+
 static int arm_smmu_device_probe(struct platform_device *pdev)
 {
        int irq, ret;
@@ -2674,7 +2692,13 @@ static int arm_smmu_device_probe(struct
platform_device *pdev)

        /* Base address */
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

+       /*
+     * Setting page0_reg_only flag, for Cavium CN99xx implementations
+     * which doesn't support the page 1 SMMU register space.
+     */
+       if (resource_size(res) == SZ_64K)
+                       page0_reg_only = true;
-        if (resource_size(res) + 1 < SZ_128K) {
+       if (resource_size(res) + 1 < arm_smmu_resource_size()) {
                dev_err(dev, "MMIO region too small (%pr)\n", res);
                return -EINVAL;
        }


Thank you,
Geetha.

On Thu, Apr 27, 2017 at 10:30 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
>> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
>> > +   /*
>> > +    * Override the size, for Cavium CN99xx implementations
>> > +    * which doesn't support the page 1 SMMU register space.
>> > +    */
>> > +   cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
>> > +   if (cpu_model == MIDR_THUNDERX_99XX ||
>> > +       cpu_model == MIDR_BRCM_VULCAN)
>> > +           size = SZ_64K;
>>
>> If you're trying to identify an SMMU erratum, identify the SMMU, not the
>> CPU it happens to be paired with this time.
>>
>> There are ID registers in the SMMU you can use to do so.
>>
>> NAK to using the CPU ID here.
>
> Agreed. I had some off-list discussion with Geetha where we agreed to use
> the "silicon ID", which I assumed was the SMMU IIDR register.
>
> Will

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#1634839

FromWill Deacon <will.deacon@arm.com>
Date2017-05-03 11:50 +0200
Message-ID<tCZ4Z-3pc-1@gated-at.bofh.it>
In reply to#1634167
Hi Geetha,

On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.

Urgh, that's unfortunate. In what way is it broken?

> If using MIDR is not accepted, can we enable errata based on SMMU resource size?
> some thing like below.

No, you need to get your model number added to IORT after all if the IIDR
can't uniqely identify the part.

Sorry,

Will

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#1634858

FromGeetha Akula <geethasowjanya.akula@gmail.com>
Date2017-05-03 12:40 +0200
Message-ID<tCZRo-41a-5@gated-at.bofh.it>
In reply to#1634839
Hi Will,

We will resubmit the patches based on IORT.


Thank you,
Geetha.

On Wed, May 3, 2017 at 3:17 PM, Will Deacon <will.deacon@arm.com> wrote:
> Hi Geetha,
>
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
>
> Urgh, that's unfortunate. In what way is it broken?
>
>> If using MIDR is not accepted, can we enable errata based on SMMU resource size?
>> some thing like below.
>
> No, you need to get your model number added to IORT after all if the IIDR
> can't uniqely identify the part.
>
> Sorry,
>
> Will

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#1636085

FromJon Masters <jcm@jonmasters.org>
Date2017-05-05 01:40 +0200
Message-ID<tDyvL-1QX-1@gated-at.bofh.it>
In reply to#1634839
On 05/03/2017 05:47 AM, Will Deacon wrote:
> Hi Geetha,
> 
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
> 
> Urgh, that's unfortunate. In what way is it broken?
> 
>> If using MIDR is not accepted, can we enable errata based on SMMU resource size?
>> some thing like below.
> 
> No, you need to get your model number added to IORT after all if the IIDR
> can't uniqely identify the part.
> 
> Sorry

[I've pinged the IORT author directly with a copy of the above message]

Can folks please take action urgently if the IORT spec needs updating to
accommodate additional vendor IDs.

Jon.

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