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Groups > linux.kernel > #1634839
| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 |
| Date | 2017-05-03 11:50 +0200 |
| Message-ID | <tCZ4Z-3pc-1@gated-at.bofh.it> (permalink) |
| References | <tARlf-13j-3@gated-at.bofh.it> <tAUMa-3dZ-13@gated-at.bofh.it> <tAUMa-3dZ-11@gated-at.bofh.it> <tAV5v-3A6-9@gated-at.bofh.it> <tCzDz-2Il-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Hi Geetha, On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote: > SMMU_IIDR register is broken on T99, that the reason we are using MIDR. Urgh, that's unfortunate. In what way is it broken? > If using MIDR is not accepted, can we enable errata based on SMMU resource size? > some thing like below. No, you need to get your model number added to IORT after all if the IIDR can't uniqely identify the part. Sorry, Will
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Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Mark Rutland <mark.rutland@arm.com> - 2017-04-27 18:50 +0200
Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Will Deacon <will.deacon@arm.com> - 2017-04-27 19:10 +0200
Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha Akula <geethasowjanya.akula@gmail.com> - 2017-05-02 08:40 +0200
Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Will Deacon <will.deacon@arm.com> - 2017-05-03 11:50 +0200
Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha Akula <geethasowjanya.akula@gmail.com> - 2017-05-03 12:40 +0200
Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Jon Masters <jcm@jonmasters.org> - 2017-05-05 01:40 +0200
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