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[PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

Started byGrzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
First post2016-11-01 11:20 +0100
Last post2016-11-07 22:00 +0100
Articles 5 — 4 participants

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  [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-11-01 11:20 +0100
    Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and  PHIR3MWAIT bit Borislav Petkov <bp@suse.de> - 2016-11-03 16:00 +0100
    Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and  PHIR3MWAIT bit Thomas Gleixner <tglx@linutronix.de> - 2016-11-03 18:10 +0100
      RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and  PHIR3MWAIT bit "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-11-04 07:50 +0100
        RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and  PHIR3MWAIT bit Thomas Gleixner <tglx@linutronix.de> - 2016-11-07 22:00 +0100

#1513192 — [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

FromGrzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Date2016-11-01 11:20 +0100
Subject[PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Message-ID<syEkF-7nA-1@gated-at.bofh.it>
Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
MONITOR and MWAIT instructions outside of ring 0.

The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
Setting bit 1 of this register enables it, so MONITOR and MWAIT
instructions do not cause invalid-opcode exceptions when invoked
outside of ring 0.
The feature MSR is not yet documented in the SDM. Here is
the relevant documentation:

Hex   Dec  Name                    Scope
140H  320  MISC_FEATURE_ENABLES    Thread
           0    Reserved
           1    if set to 1, the MONITOR and MWAIT instructions do not
                cause invalid-opcode exceptions when executed with CPL > 0
                or in virtual-8086 mode. If MWAIT is executed when CPL > 0
                or in virtual-8086 mode, and if EAX indicates a C-state
                other than C0 or C1, the instruction operates as if EAX
                indicated the C-state C1.
           63:2 Reserved

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 arch/x86/include/asm/msr-index.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 56f4c66..0fc220d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -540,6 +540,11 @@
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
+/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
+#define MSR_MISC_FEATURE_ENABLES	0x00000140
+#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT	1
+#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT	(1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
+
 #define MSR_IA32_TSC_DEADLINE		0x000006E0
 
 /* P4/Xeon+ specific */
-- 
2.5.1

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#1514568 — Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

FromBorislav Petkov <bp@suse.de>
Date2016-11-03 16:00 +0100
SubjectRe: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Message-ID<szrEP-5cN-29@gated-at.bofh.it>
In reply to#1513192
On Tue, Nov 01, 2016 at 11:14:47AM +0100, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
> MONITOR and MWAIT instructions outside of ring 0.
> 
> The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
> Setting bit 1 of this register enables it, so MONITOR and MWAIT
> instructions do not cause invalid-opcode exceptions when invoked
> outside of ring 0.
> The feature MSR is not yet documented in the SDM. Here is
> the relevant documentation:
> 
> Hex   Dec  Name                    Scope
> 140H  320  MISC_FEATURE_ENABLES    Thread
>            0    Reserved
>            1    if set to 1, the MONITOR and MWAIT instructions do not
>                 cause invalid-opcode exceptions when executed with CPL > 0
>                 or in virtual-8086 mode. If MWAIT is executed when CPL > 0
>                 or in virtual-8086 mode, and if EAX indicates a C-state
>                 other than C0 or C1, the instruction operates as if EAX
>                 indicated the C-state C1.
>            63:2 Reserved
> 
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
> ---
>  arch/x86/include/asm/msr-index.h | 5 +++++
>  1 file changed, 5 insertions(+)

Reviewed-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--

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#1514704 — Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

FromThomas Gleixner <tglx@linutronix.de>
Date2016-11-03 18:10 +0100
SubjectRe: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Message-ID<sztGy-6N2-13@gated-at.bofh.it>
In reply to#1513192
On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>  
> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */

Oh well. I asked you to make that whole PHI thing go away.

This is a feature which has nothing to do with PHI. It just happens to be
implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.

It's all about a feature which enables ring 3 mwait/monitor.

> +#define MSR_MISC_FEATURE_ENABLES	0x00000140
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT	1
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT	(1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
> +

You really try hard to get your crap behind me. Stop sending out half baken
shit every other day without addressing my review comments.

Your trust level approaches negative space.

Thanks,

	tglx

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#1515032 — RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

From"Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com>
Date2016-11-04 07:50 +0100
SubjectRE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Message-ID<szGu5-6zz-13@gated-at.bofh.it>
In reply to#1514704
>>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>>  
>> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
>
>Oh well. I asked you to make that whole PHI thing go away. 
>
>This is a feature which has nothing to do with PHI. It just happens to be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.
>
>It's all about a feature which enables ring 3 mwait/monitor.

This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved for other architectures.
I think this will be confusing when I remove PHI.

>> +#define MSR_MISC_FEATURE_ENABLES	0x00000140
>> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT	1
>> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT	(1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
>> +
>
>You really try hard to get your crap behind me. Stop sending out half baken shit every other day without addressing my review comments.
>
>Your trust level approaches negative space. 
>
>Thanks,
>
>	tglx

Regards,
Grzegorz

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#1516581 — RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

FromThomas Gleixner <tglx@linutronix.de>
Date2016-11-07 22:00 +0100
SubjectRE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Message-ID<sAZbj-8hx-5@gated-at.bofh.it>
In reply to#1515032
On Fri, 4 Nov 2016, Andrejczuk, Grzegorz wrote:
> >>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
> >>  
> >> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
> >
> > Oh well. I asked you to make that whole PHI thing go away. 
> >
> > This is a feature which has nothing to do with PHI. It just happens to
> > be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI
> > specific.
> > It's all about a feature which enables ring 3 mwait/monitor.
> 
> This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved
> for other architectures.  I think this will be confusing when I remove
> PHI.

It's reserved for other models simply because they do not implement it.

PHI is nothing special and the MSR is not PHI specific at all. It's used
for other features on other models, e.g. CPUID faulting (bit 0). That's
why PHI got bit 1.

Intel has so far been very consistent with MSRs which are implemented on
different models and it would be highly surprising if they would use a
different MSR/BIT when they bring that ring3 mwait feature to other models
than PHI. We make it PHI special when that happens, but for now there is
nothing PHI special, except that the only model which implements this is
PHI at the moment.

Thanks,

	tglx

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