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Groups > linux.kernel > #1488081 > unrolled thread

[PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver

Started byAbhishek Sahu <absahu@codeaurora.org>
First post2016-09-21 14:30 +0200
Last post2016-09-21 14:30 +0200
Articles 3 — 1 participant

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  [PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver Abhishek Sahu <absahu@codeaurora.org> - 2016-09-21 14:30 +0200
    [PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name Abhishek Sahu <absahu@codeaurora.org> - 2016-09-21 14:30 +0200
    [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll Abhishek Sahu <absahu@codeaurora.org> - 2016-09-21 14:30 +0200

#1488081 — [PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver

FromAbhishek Sahu <absahu@codeaurora.org>
Date2016-09-21 14:30 +0200
Subject[PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver
Message-ID<sjOOZ-vu-5@gated-at.bofh.it>
These patches are related to Qualcomm IPQ4019 GCC (Global Clock
Controller) driver code mainly adding the nodes for clock marked
as fixed in current IPQ4019 clock driver and support for multiple
CPU frequencies.

[V3]

   1. Addressed the review comments given in v2 patches.
   2. Replaced the do_div with normal division.
   3. Marked the PCNOC node as critical.
   4. Modified the frequency values for the recent change done
      in IPQ4019 bootloader.
   5. Changed the i2c node frequency table for 19.05 MHz clock.

[V2]

   1. Removed the fixed clock references and add the same as clock nodes
   with recalc_rate operation.
   2. Added all the supported cpu frequencies in frequency table.

Abhishek Sahu (7):
  clk: qcom: ipq4019: Added the clock nodes and operations for pll
  clk: qcom: ipq4019: Added the apss cpu pll divider clock node
  clk: qcom: ipq4019: Added the nodes for pcnoc
  clk: qcom: ipq4019: Added all the frequencies for apps cpu
  clk: qcom: ipq4019: corrected sdcc frequency and parent name
  clk: qcom: ipq4019: changed the frequency value for ddr pll
  clk: qcom: ipq4019: changed i2c freq table

 drivers/clk/qcom/gcc-ipq4019.c               | 489 +++++++++++++++++++++++++--
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |  11 +
 2 files changed, 477 insertions(+), 23 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1488083 — [PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name

FromAbhishek Sahu <absahu@codeaurora.org>
Date2016-09-21 14:30 +0200
Subject[PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name
Message-ID<sjOP0-vu-21@gated-at.bofh.it>
In reply to#1488081
1. The parent for sdcc clock is sdccpll so corrected the same
   in its parent map.
2. The frequency value was wrong so changed to correct
   frequency.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 160e0cf..b2decd5 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -120,7 +120,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
 
 static const char * const gcc_xo_sdcc1_500[] = {
 	"xo",
-	"ddrpll",
+	"ddrpllsdcc",
 	"fepll500",
 };
 
@@ -540,13 +540,13 @@ static struct clk_branch gcc_gp3_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
-	F(144000,    P_XO,			1,  3, 240),
-	F(400000,    P_XO,			1,  1, 0),
-	F(20000000,  P_FEPLL500,		1,  1, 25),
-	F(25000000,  P_FEPLL500,		1,  1, 20),
-	F(50000000,  P_FEPLL500,		1,  1, 10),
-	F(100000000, P_FEPLL500,		1,  1, 5),
-	F(193000000, P_DDRPLL,		1,  0, 0),
+	F(144000,    P_XO,       1,  3, 240),
+	F(400000,    P_XO,       1,  1, 0),
+	F(20000000,  P_FEPLL500, 1,  1, 25),
+	F(25000000,  P_FEPLL500, 1,  1, 20),
+	F(50000000,  P_FEPLL500, 1,  1, 10),
+	F(100000000, P_FEPLL500, 1,  1, 5),
+	F(190000000, P_DDRPLL,   1,  0, 0),
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1488084 — [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll

FromAbhishek Sahu <absahu@codeaurora.org>
Date2016-09-21 14:30 +0200
Subject[PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll
Message-ID<sjOP0-vu-33@gated-at.bofh.it>
In reply to#1488081
The feedback divider for DDR PLL has been changed in IPQ4019
bootloader from 111 to 112 so changed the frequency values
for the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 52 +++++++++++++++++++++---------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index b2decd5..a2809db 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -546,7 +546,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
 	F(25000000,  P_FEPLL500, 1,  1, 20),
 	F(50000000,  P_FEPLL500, 1,  1, 10),
 	F(100000000, P_FEPLL500, 1,  1, 5),
-	F(190000000, P_DDRPLL,   1,  0, 0),
+	F(192000000, P_DDRPLL,   1,  0, 0),
 	{ }
 };
 
@@ -567,18 +567,18 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
 	F(48000000,  P_XO,         1, 0, 0),
 	F(200000000, P_FEPLL200,   1, 0, 0),
-	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(384000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(413000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(448000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(488000000, P_DDRPLLAPSS, 1, 0, 0),
 	F(500000000, P_FEPLL500,   1, 0, 0),
-	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
-	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(512000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(537000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(565000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(597000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(632000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(672000000, P_DDRPLLAPSS, 1, 0, 0),
+	F(716000000, P_DDRPLLAPSS, 1, 0, 0),
 	{ }
 };
 
@@ -1381,20 +1381,20 @@ static const struct clk_ops clk_regmap_cpu_div_ops = {
 };
 
 static const struct freq_tbl ftbl_apps_ddr_pll[] = {
-	{ 380000000, P_XO, 0xd, 0, 0 },
-	{ 409000000, P_XO, 0xc, 0, 0 },
-	{ 444000000, P_XO, 0xb, 0, 0 },
-	{ 484000000, P_XO, 0xa, 0, 0 },
-	{ 507000000, P_XO, 0x9, 0, 0 },
-	{ 532000000, P_XO, 0x8, 0, 0 },
-	{ 560000000, P_XO, 0x7, 0, 0 },
-	{ 592000000, P_XO, 0x6, 0, 0 },
-	{ 626000000, P_XO, 0x5, 0, 0 },
-	{ 666000000, P_XO, 0x4, 0, 0 },
-	{ 710000000, P_XO, 0x3, 0, 0 },
-	{ 761000000, P_XO, 0x2, 0, 0 },
-	{ 819000000, P_XO, 0x1, 0, 0 },
-	{ 888000000, P_XO, 0x0, 0, 0 },
+	{ 384000000, P_XO, 0xd, 0, 0 },
+	{ 413000000, P_XO, 0xc, 0, 0 },
+	{ 448000000, P_XO, 0xb, 0, 0 },
+	{ 488000000, P_XO, 0xa, 0, 0 },
+	{ 512000000, P_XO, 0x9, 0, 0 },
+	{ 537000000, P_XO, 0x8, 0, 0 },
+	{ 565000000, P_XO, 0x7, 0, 0 },
+	{ 597000000, P_XO, 0x6, 0, 0 },
+	{ 632000000, P_XO, 0x5, 0, 0 },
+	{ 672000000, P_XO, 0x4, 0, 0 },
+	{ 716000000, P_XO, 0x3, 0, 0 },
+	{ 768000000, P_XO, 0x2, 0, 0 },
+	{ 823000000, P_XO, 0x1, 0, 0 },
+	{ 896000000, P_XO, 0x0, 0, 0 },
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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