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[PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name

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1. The parent for sdcc clock is sdccpll so corrected the same
   in its parent map.
2. The frequency value was wrong so changed to correct
   frequency.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 160e0cf..b2decd5 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -120,7 +120,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
 
 static const char * const gcc_xo_sdcc1_500[] = {
 	"xo",
-	"ddrpll",
+	"ddrpllsdcc",
 	"fepll500",
 };
 
@@ -540,13 +540,13 @@ static struct clk_branch gcc_gp3_clk = {
 };
 
 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
-	F(144000,    P_XO,			1,  3, 240),
-	F(400000,    P_XO,			1,  1, 0),
-	F(20000000,  P_FEPLL500,		1,  1, 25),
-	F(25000000,  P_FEPLL500,		1,  1, 20),
-	F(50000000,  P_FEPLL500,		1,  1, 10),
-	F(100000000, P_FEPLL500,		1,  1, 5),
-	F(193000000, P_DDRPLL,		1,  0, 0),
+	F(144000,    P_XO,       1,  3, 240),
+	F(400000,    P_XO,       1,  1, 0),
+	F(20000000,  P_FEPLL500, 1,  1, 25),
+	F(25000000,  P_FEPLL500, 1,  1, 20),
+	F(50000000,  P_FEPLL500, 1,  1, 10),
+	F(100000000, P_FEPLL500, 1,  1, 5),
+	F(190000000, P_DDRPLL,   1,  0, 0),
 	{ }
 };
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH v3 0/7] Patches for QCOM IPQ4019 clock driver Abhishek Sahu <absahu@codeaurora.org> - 2016-09-21 14:30 +0200
  [PATCH v3 5/7] clk: qcom: ipq4019: corrected sdcc frequency and parent name Abhishek Sahu <absahu@codeaurora.org> - 2016-09-21 14:30 +0200
  [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll Abhishek Sahu <absahu@codeaurora.org> - 2016-09-21 14:30 +0200

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