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Groups > linux.kernel > #1472280 > unrolled thread
| Started by | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| First post | 2016-08-30 10:00 +0200 |
| Last post | 2016-09-07 17:00 +0200 |
| Articles | 20 on this page of 21 — 5 participants |
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[PATCH v3 0/8] aspeed: Add pinctrl and gpio drivers Andrew Jeffery <andrew@aj.id.au> - 2016-08-30 10:00 +0200
[PATCH v3 7/8] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery <andrew@aj.id.au> - 2016-08-30 10:00 +0200
Re: [PATCH v3 7/8] pinctrl: Add pinctrl-aspeed-g5 driver Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 17:00 +0200
[PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings Andrew Jeffery <andrew@aj.id.au> - 2016-08-30 10:00 +0200
Re: [PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 16:40 +0200
Re: [PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings Arnd Bergmann <arnd@arndb.de> - 2016-09-07 16:50 +0200
[PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery <andrew@aj.id.au> - 2016-08-30 10:00 +0200
Re: [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Rob Herring <robh@kernel.org> - 2016-09-02 17:10 +0200
Re: [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 16:50 +0200
Re: [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery <andrew@aj.id.au> - 2016-09-08 03:20 +0200
[PATCH v3 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery <andrew@aj.id.au> - 2016-08-30 10:00 +0200
Re: [PATCH v3 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 16:50 +0200
[PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery <andrew@aj.id.au> - 2016-08-30 10:00 +0200
Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 16:40 +0200
Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Lee Jones <lee.jones@linaro.org> - 2016-09-07 18:30 +0200
Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery <andrew@aj.id.au> - 2016-09-08 03:10 +0200
Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery <andrew@aj.id.au> - 2016-09-08 03:10 +0200
Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units Lee Jones <lee.jones@linaro.org> - 2016-09-08 09:10 +0200
Re: [PATCH v3 5/8] pinctrl: Add core support for Aspeed SoCs Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 17:00 +0200
Re: [PATCH v3 5/8] pinctrl: Add core support for Aspeed SoCs Andrew Jeffery <andrew@aj.id.au> - 2016-09-08 06:00 +0200
Re: [PATCH v3 6/8] pinctrl: Add pinctrl-aspeed-g4 driver Linus Walleij <linus.walleij@linaro.org> - 2016-09-07 17:00 +0200
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-08-30 10:00 +0200 |
| Subject | [PATCH v3 0/8] aspeed: Add pinctrl and gpio drivers |
| Message-ID | <sbM7D-1Ul-3@gated-at.bofh.it> |
Hi all, Here's v3 of the Aspeed pinctrl and gpio driver patches, which aims to address the review comments on v2: https://lkml.org/lkml/2016/8/19/394 The combined series has been tested with both the AST2400 (g4) and AST2500 (g5) SoCs on OpenPOWER Palmetto and Aspeed AST2500 EVB machines respectively, and similarly in QEMU with the palmetto-bmc and ast2500-evb machines[1]. Since v2: * Add interrupt-controller as a required property to gpio devicetree node * Drop unit address in pinctrl devicetree example * PINCTRL_ASPEED depends on MFD_SYSCON rather than selecting it * Use regmap_update_bits() where possible Since v1: * Split the series in two: driver and SoC patches. * Update devicetree bindings documentation * Add documentation for aspeed pinctrl core functions * Fix bugs in existing signal descriptors * Add a number of pin and mux function declarations * Provide debug information on unexpected conditions Cheers, Andrew [1] https://lists.gnu.org/archive/html/qemu-arm/2016-08/msg00019.html --- Andrew Jeffery (7): MAINTAINERS: Add glob for Aspeed devicetree bindings syscon: dt-bindings: Add documentation for Aspeed system control units pinctrl: dt-bindings: Add documentation for Aspeed pin controllers gpio: dt-bindings: Add documentation for Aspeed GPIO controllers pinctrl: Add core support for Aspeed SoCs pinctrl: Add pinctrl-aspeed-g4 driver pinctrl: Add pinctrl-aspeed-g5 driver Joel Stanley (1): gpio: Add Aspeed driver .../devicetree/bindings/gpio/gpio-aspeed.txt | 36 + .../devicetree/bindings/mfd/aspeed-scu.txt | 18 + .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 65 ++ MAINTAINERS | 2 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-aspeed.c | 457 ++++++++ drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Kconfig | 24 + drivers/pinctrl/aspeed/Makefile | 6 + drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1231 ++++++++++++++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 808 +++++++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.c | 498 ++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.h | 569 +++++++++ 15 files changed, 3724 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-aspeed.txt create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-scu.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt create mode 100644 drivers/gpio/gpio-aspeed.c create mode 100644 drivers/pinctrl/aspeed/Kconfig create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.c create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.h -- 2.9.3.1.g0db844e
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-08-30 10:00 +0200 |
| Subject | [PATCH v3 7/8] pinctrl: Add pinctrl-aspeed-g5 driver |
| Message-ID | <sbM7D-1Ul-9@gated-at.bofh.it> |
| In reply to | #1472280 |
A small subset of pins and functions are exposed. The selection of pins
and functions is driven by the development of OpenBMC[1] on the
AST2500 SoC, particularly around booting the IBM Witherspoon platform.
[1] https://github.com/openbmc/docs
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---
drivers/pinctrl/aspeed/Kconfig | 8 +
drivers/pinctrl/aspeed/Makefile | 1 +
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 808 +++++++++++++++++++++++++++++
3 files changed, 817 insertions(+)
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
index 1f3d74549381..998eabef3a65 100644
--- a/drivers/pinctrl/aspeed/Kconfig
+++ b/drivers/pinctrl/aspeed/Kconfig
@@ -14,3 +14,11 @@ config PINCTRL_ASPEED_G4
help
Say Y here to enable pin controller support for Aspeed's 4th
generation SoCs. GPIO is provided by a separate GPIO driver.
+
+config PINCTRL_ASPEED_G5
+ bool "Aspeed G5 SoC pin control"
+ depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF
+ select PINCTRL_ASPEED
+ help
+ Say Y here to enable pin controller support for Aspeed's 5th
+ generation SoCs. GPIO is provided by a separate GPIO driver.
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
index 8675d6fd82df..191ed0fc1804 100644
--- a/drivers/pinctrl/aspeed/Makefile
+++ b/drivers/pinctrl/aspeed/Makefile
@@ -3,3 +3,4 @@
ccflags-y += -Woverride-init
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
+obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
new file mode 100644
index 000000000000..e1ab864e1a7f
--- /dev/null
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -0,0 +1,808 @@
+/*
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/bitops.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-aspeed.h"
+
+#define ASPEED_G5_NR_PINS 228
+
+#define COND1 SIG_DESC_BIT(SCU90, 6, 0)
+#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
+
+#define B14 0
+SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
+
+#define E13 3
+SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
+
+#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
+
+#define C14 4
+SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
+MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5);
+
+FUNC_GROUP_DECL(TIMER5, C14);
+
+#define A13 5
+SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
+MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
+
+FUNC_GROUP_DECL(TIMER6, A13);
+
+FUNC_GROUP_DECL(I2C9, C14, A13);
+
+#define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
+
+#define C13 6
+SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
+MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7);
+
+FUNC_GROUP_DECL(TIMER7, C13);
+
+#define B13 7
+SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
+MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8);
+
+FUNC_GROUP_DECL(TIMER8, B13);
+
+FUNC_GROUP_DECL(MDIO2, C13, B13);
+
+#define H20 15
+GPIO_PIN_DECL(H20, GPIOB7);
+
+#define SD1_DESC SIG_DESC_SET(SCU90, 0)
+
+#define C12 16
+#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
+SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
+MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10);
+
+#define A12 17
+SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
+MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10);
+
+FUNC_GROUP_DECL(I2C10, C12, A12);
+
+#define B12 18
+#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
+MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11);
+
+#define D9 19
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
+MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11);
+
+FUNC_GROUP_DECL(I2C11, B12, D9);
+
+#define D10 20
+#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
+MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12);
+
+#define E12 21
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
+MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12);
+
+FUNC_GROUP_DECL(I2C12, D10, E12);
+
+#define C11 22
+#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
+SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
+MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13);
+
+#define B11 23
+SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
+MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13);
+
+FUNC_GROUP_DECL(I2C13, C11, B11);
+FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
+
+#define SD2_DESC SIG_DESC_SET(SCU90, 1)
+#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
+#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
+
+#define F19 24
+SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
+SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
+MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN);
+
+#define E21 25
+SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
+SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
+MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT);
+
+FUNC_GROUP_DECL(GPID0, F19, E21);
+
+#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
+
+#define D20 26
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
+SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
+MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID2IN);
+
+#define D21 27
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
+SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
+MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID2OUT);
+
+FUNC_GROUP_DECL(GPID2, D20, D21);
+
+#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
+#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
+
+#define B20 32
+SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
+SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
+SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
+MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
+
+#define C20 33
+SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
+SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
+SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
+MS_PIN_DECL(C20, GPIE0, NDCD3, GPIE0OUT);
+
+FUNC_GROUP_DECL(GPIE0, B20, C20);
+
+#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13)
+#define C18 64
+SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC);
+SS_PIN_DECL(C18, GPIOI0, SYSCS);
+
+#define E15 65
+SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC);
+SS_PIN_DECL(E15, GPIOI1, SYSCK);
+
+#define A14 66
+SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC);
+SS_PIN_DECL(A14, GPIOI2, SYSMOSI);
+
+#define C16 67
+SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC);
+SS_PIN_DECL(C16, GPIOI3, SYSMISO);
+
+FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16);
+
+#define L2 73
+SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
+SS_PIN_DECL(L2, GPIOJ1, SGPMLD);
+
+#define N3 74
+SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
+SS_PIN_DECL(N3, GPIOJ2, SGPMO);
+
+#define N4 75
+SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
+SS_PIN_DECL(N4, GPIOJ3, SGPMI);
+
+#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
+
+#define L3 80
+SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
+SS_PIN_DECL(L3, GPIOK0, SCL5);
+
+#define L4 81
+SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
+SS_PIN_DECL(L4, GPIOK1, SDA5);
+
+FUNC_GROUP_DECL(I2C5, L3, L4);
+
+#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
+
+#define L1 82
+SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
+SS_PIN_DECL(L1, GPIOK2, SCL6);
+
+#define N2 83
+SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
+SS_PIN_DECL(N2, GPIOK3, SDA6);
+
+FUNC_GROUP_DECL(I2C6, L1, N2);
+
+#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
+
+#define N1 84
+SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
+SS_PIN_DECL(N1, GPIOK4, SCL7);
+
+#define P1 85
+SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
+SS_PIN_DECL(P1, GPIOK5, SDA7);
+
+FUNC_GROUP_DECL(I2C7, N1, P1);
+
+#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
+
+#define P2 86
+SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
+SS_PIN_DECL(P2, GPIOK6, SCL8);
+
+#define R1 87
+SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
+SS_PIN_DECL(R1, GPIOK7, SDA8);
+
+FUNC_GROUP_DECL(I2C8, P2, R1);
+
+#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 }
+#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 }
+#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
+#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 }
+
+#define V2 104
+#define V2_DESC SIG_DESC_SET(SCU88, 0)
+SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2);
+MS_PIN_DECL(V2, GPION0, DASHN0, PWM0);
+FUNC_GROUP_DECL(PWM0, V2);
+
+#define W2 105
+#define W2_DESC SIG_DESC_SET(SCU88, 1)
+SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2);
+MS_PIN_DECL(W2, GPION1, DASHN1, PWM1);
+FUNC_GROUP_DECL(PWM1, W2);
+
+#define V3 106
+#define V3_DESC SIG_DESC_SET(SCU88, 2)
+SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
+SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2);
+MS_PIN_DECL(V3, GPION2, VPIG2, PWM2);
+FUNC_GROUP_DECL(PWM2, V3);
+
+#define U3 107
+#define U3_DESC SIG_DESC_SET(SCU88, 3)
+SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
+SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2);
+MS_PIN_DECL(U3, GPION3, VPIG3, PWM3);
+FUNC_GROUP_DECL(PWM3, U3);
+
+#define W3 108
+#define W3_DESC SIG_DESC_SET(SCU88, 4)
+SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
+SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2);
+MS_PIN_DECL(W3, GPION4, VPIG4, PWM4);
+FUNC_GROUP_DECL(PWM4, W3);
+
+#define AA3 109
+#define AA3_DESC SIG_DESC_SET(SCU88, 5)
+SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
+SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2);
+MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5);
+FUNC_GROUP_DECL(PWM5, AA3);
+
+#define Y3 110
+#define Y3_DESC SIG_DESC_SET(SCU88, 6)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2);
+MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6);
+FUNC_GROUP_DECL(PWM6, Y3);
+
+#define T4 111
+#define T4_DESC SIG_DESC_SET(SCU88, 7)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
+MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
+FUNC_GROUP_DECL(PWM7, T4);
+
+#define V6 127
+SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
+ SIG_DESC_SET(SCU88, 23));
+SS_PIN_DECL(V6, GPIOP7, DASHV6);
+
+#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
+
+#define A11 128
+SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
+SS_PIN_DECL(A11, GPIOQ0, SCL3);
+
+#define A10 129
+SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
+SS_PIN_DECL(A10, GPIOQ1, SDA3);
+
+FUNC_GROUP_DECL(I2C3, A11, A10);
+
+#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
+
+#define A9 130
+SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
+SS_PIN_DECL(A9, GPIOQ2, SCL4);
+
+#define B9 131
+SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
+SS_PIN_DECL(B9, GPIOQ3, SDA4);
+
+FUNC_GROUP_DECL(I2C4, A9, B9);
+
+#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
+
+#define N21 132
+SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
+SS_PIN_DECL(N21, GPIOQ4, SCL14);
+
+#define N22 133
+SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
+SS_PIN_DECL(N22, GPIOQ5, SDA14);
+
+FUNC_GROUP_DECL(I2C14, N21, N22);
+
+#define B10 134
+SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
+
+#define N20 135
+SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
+
+#define D8 142
+SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
+SS_PIN_DECL(D8, GPIOR6, MDC1);
+
+#define E10 143
+SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
+SS_PIN_DECL(E10, GPIOR7, MDIO1);
+
+FUNC_GROUP_DECL(MDIO1, D8, E10);
+
+/* RGMII1/RMII1 */
+
+#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
+#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
+
+#define B5 152
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC,
+ SIG_DESC_SET(SCU48, 29));
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
+MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO),
+ SIG_EXPR_LIST_PTR(RGMII1TXCK));
+
+#define E9 153
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
+MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN),
+ SIG_EXPR_LIST_PTR(RGMII1TXCTL));
+
+#define F9 154
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
+MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
+ SIG_EXPR_LIST_PTR(RGMII1TXD0));
+
+#define A5 155
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
+MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
+ SIG_EXPR_LIST_PTR(RGMII1TXD1));
+
+#define E7 156
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
+MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0),
+ SIG_EXPR_LIST_PTR(RGMII1TXD2));
+
+#define D7 157
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
+MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1),
+ SIG_EXPR_LIST_PTR(RGMII1TXD3));
+
+#define B2 158
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC,
+ SIG_DESC_SET(SCU48, 30));
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
+MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO),
+ SIG_EXPR_LIST_PTR(RGMII2TXCK));
+
+#define B1 159
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
+MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN),
+ SIG_EXPR_LIST_PTR(RGMII2TXCTL));
+
+#define A2 160
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
+MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
+ SIG_EXPR_LIST_PTR(RGMII2TXD0));
+
+#define B3 161
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
+MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
+ SIG_EXPR_LIST_PTR(RGMII2TXD1));
+
+#define D5 162
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
+MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0),
+ SIG_EXPR_LIST_PTR(RGMII2TXD2));
+
+#define D4 163
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
+MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1),
+ SIG_EXPR_LIST_PTR(RGMII2TXD3));
+
+#define B4 164
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
+MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI),
+ SIG_EXPR_LIST_PTR(RGMII1RXCK));
+
+#define A4 165
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
+MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2),
+ SIG_EXPR_LIST_PTR(RGMII1RXCTL));
+
+#define A3 166
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
+MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
+ SIG_EXPR_LIST_PTR(RGMII1RXD0));
+
+#define D6 167
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
+MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
+ SIG_EXPR_LIST_PTR(RGMII1RXD1));
+
+#define C5 168
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
+MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
+ SIG_EXPR_LIST_PTR(RGMII1RXD2));
+
+#define C4 169
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
+MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
+ SIG_EXPR_LIST_PTR(RGMII1RXD3));
+
+FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
+FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
+
+#define C2 170
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
+MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI),
+ SIG_EXPR_LIST_PTR(RGMII2RXCK));
+
+#define C1 171
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
+MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2),
+ SIG_EXPR_LIST_PTR(RGMII2RXCTL));
+
+#define C3 172
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
+MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
+ SIG_EXPR_LIST_PTR(RGMII2RXD0));
+
+#define D1 173
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
+MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
+ SIG_EXPR_LIST_PTR(RGMII2RXD1));
+
+#define D2 174
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
+MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
+ SIG_EXPR_LIST_PTR(RGMII2RXD2));
+
+#define E6 175
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
+MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
+ SIG_EXPR_LIST_PTR(RGMII2RXD3));
+
+FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
+FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
+
+/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
+
+static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
+ ASPEED_PINCTRL_PIN(A10),
+ ASPEED_PINCTRL_PIN(A11),
+ ASPEED_PINCTRL_PIN(A12),
+ ASPEED_PINCTRL_PIN(A13),
+ ASPEED_PINCTRL_PIN(A14),
+ ASPEED_PINCTRL_PIN(A2),
+ ASPEED_PINCTRL_PIN(A3),
+ ASPEED_PINCTRL_PIN(A4),
+ ASPEED_PINCTRL_PIN(A5),
+ ASPEED_PINCTRL_PIN(A9),
+ ASPEED_PINCTRL_PIN(AA3),
+ ASPEED_PINCTRL_PIN(B1),
+ ASPEED_PINCTRL_PIN(B10),
+ ASPEED_PINCTRL_PIN(B11),
+ ASPEED_PINCTRL_PIN(B12),
+ ASPEED_PINCTRL_PIN(B13),
+ ASPEED_PINCTRL_PIN(B14),
+ ASPEED_PINCTRL_PIN(B2),
+ ASPEED_PINCTRL_PIN(B20),
+ ASPEED_PINCTRL_PIN(B3),
+ ASPEED_PINCTRL_PIN(B4),
+ ASPEED_PINCTRL_PIN(B5),
+ ASPEED_PINCTRL_PIN(B9),
+ ASPEED_PINCTRL_PIN(C1),
+ ASPEED_PINCTRL_PIN(C11),
+ ASPEED_PINCTRL_PIN(C12),
+ ASPEED_PINCTRL_PIN(C13),
+ ASPEED_PINCTRL_PIN(C14),
+ ASPEED_PINCTRL_PIN(C16),
+ ASPEED_PINCTRL_PIN(C18),
+ ASPEED_PINCTRL_PIN(C2),
+ ASPEED_PINCTRL_PIN(C20),
+ ASPEED_PINCTRL_PIN(C3),
+ ASPEED_PINCTRL_PIN(C4),
+ ASPEED_PINCTRL_PIN(C5),
+ ASPEED_PINCTRL_PIN(D1),
+ ASPEED_PINCTRL_PIN(D10),
+ ASPEED_PINCTRL_PIN(D2),
+ ASPEED_PINCTRL_PIN(D20),
+ ASPEED_PINCTRL_PIN(D21),
+ ASPEED_PINCTRL_PIN(D4),
+ ASPEED_PINCTRL_PIN(D5),
+ ASPEED_PINCTRL_PIN(D6),
+ ASPEED_PINCTRL_PIN(D7),
+ ASPEED_PINCTRL_PIN(D8),
+ ASPEED_PINCTRL_PIN(D9),
+ ASPEED_PINCTRL_PIN(E10),
+ ASPEED_PINCTRL_PIN(E12),
+ ASPEED_PINCTRL_PIN(E13),
+ ASPEED_PINCTRL_PIN(E15),
+ ASPEED_PINCTRL_PIN(E21),
+ ASPEED_PINCTRL_PIN(E6),
+ ASPEED_PINCTRL_PIN(E7),
+ ASPEED_PINCTRL_PIN(E9),
+ ASPEED_PINCTRL_PIN(F19),
+ ASPEED_PINCTRL_PIN(F9),
+ ASPEED_PINCTRL_PIN(H20),
+ ASPEED_PINCTRL_PIN(L1),
+ ASPEED_PINCTRL_PIN(L2),
+ ASPEED_PINCTRL_PIN(L3),
+ ASPEED_PINCTRL_PIN(L4),
+ ASPEED_PINCTRL_PIN(N1),
+ ASPEED_PINCTRL_PIN(N2),
+ ASPEED_PINCTRL_PIN(N20),
+ ASPEED_PINCTRL_PIN(N21),
+ ASPEED_PINCTRL_PIN(N22),
+ ASPEED_PINCTRL_PIN(N3),
+ ASPEED_PINCTRL_PIN(N4),
+ ASPEED_PINCTRL_PIN(P1),
+ ASPEED_PINCTRL_PIN(P2),
+ ASPEED_PINCTRL_PIN(R1),
+ ASPEED_PINCTRL_PIN(T4),
+ ASPEED_PINCTRL_PIN(U3),
+ ASPEED_PINCTRL_PIN(V2),
+ ASPEED_PINCTRL_PIN(V3),
+ ASPEED_PINCTRL_PIN(V6),
+ ASPEED_PINCTRL_PIN(W2),
+ ASPEED_PINCTRL_PIN(W3),
+ ASPEED_PINCTRL_PIN(Y3),
+};
+
+static const struct aspeed_pin_group aspeed_g5_groups[] = {
+ ASPEED_PINCTRL_GROUP(GPID0),
+ ASPEED_PINCTRL_GROUP(GPID2),
+ ASPEED_PINCTRL_GROUP(GPIE0),
+ ASPEED_PINCTRL_GROUP(I2C10),
+ ASPEED_PINCTRL_GROUP(I2C11),
+ ASPEED_PINCTRL_GROUP(I2C12),
+ ASPEED_PINCTRL_GROUP(I2C13),
+ ASPEED_PINCTRL_GROUP(I2C14),
+ ASPEED_PINCTRL_GROUP(I2C3),
+ ASPEED_PINCTRL_GROUP(I2C4),
+ ASPEED_PINCTRL_GROUP(I2C5),
+ ASPEED_PINCTRL_GROUP(I2C6),
+ ASPEED_PINCTRL_GROUP(I2C7),
+ ASPEED_PINCTRL_GROUP(I2C8),
+ ASPEED_PINCTRL_GROUP(I2C9),
+ ASPEED_PINCTRL_GROUP(MAC1LINK),
+ ASPEED_PINCTRL_GROUP(MDIO1),
+ ASPEED_PINCTRL_GROUP(MDIO2),
+ ASPEED_PINCTRL_GROUP(OSCCLK),
+ ASPEED_PINCTRL_GROUP(PEWAKE),
+ ASPEED_PINCTRL_GROUP(PWM0),
+ ASPEED_PINCTRL_GROUP(PWM1),
+ ASPEED_PINCTRL_GROUP(PWM2),
+ ASPEED_PINCTRL_GROUP(PWM3),
+ ASPEED_PINCTRL_GROUP(PWM4),
+ ASPEED_PINCTRL_GROUP(PWM5),
+ ASPEED_PINCTRL_GROUP(PWM6),
+ ASPEED_PINCTRL_GROUP(PWM7),
+ ASPEED_PINCTRL_GROUP(RGMII1),
+ ASPEED_PINCTRL_GROUP(RGMII2),
+ ASPEED_PINCTRL_GROUP(RMII1),
+ ASPEED_PINCTRL_GROUP(RMII2),
+ ASPEED_PINCTRL_GROUP(SD1),
+ ASPEED_PINCTRL_GROUP(SPI1),
+ ASPEED_PINCTRL_GROUP(TIMER4),
+ ASPEED_PINCTRL_GROUP(TIMER5),
+ ASPEED_PINCTRL_GROUP(TIMER6),
+ ASPEED_PINCTRL_GROUP(TIMER7),
+ ASPEED_PINCTRL_GROUP(TIMER8),
+};
+
+static const struct aspeed_pin_function aspeed_g5_functions[] = {
+ ASPEED_PINCTRL_FUNC(GPID0),
+ ASPEED_PINCTRL_FUNC(GPID2),
+ ASPEED_PINCTRL_FUNC(GPIE0),
+ ASPEED_PINCTRL_FUNC(I2C10),
+ ASPEED_PINCTRL_FUNC(I2C11),
+ ASPEED_PINCTRL_FUNC(I2C12),
+ ASPEED_PINCTRL_FUNC(I2C13),
+ ASPEED_PINCTRL_FUNC(I2C14),
+ ASPEED_PINCTRL_FUNC(I2C3),
+ ASPEED_PINCTRL_FUNC(I2C4),
+ ASPEED_PINCTRL_FUNC(I2C5),
+ ASPEED_PINCTRL_FUNC(I2C6),
+ ASPEED_PINCTRL_FUNC(I2C7),
+ ASPEED_PINCTRL_FUNC(I2C8),
+ ASPEED_PINCTRL_FUNC(I2C9),
+ ASPEED_PINCTRL_FUNC(MAC1LINK),
+ ASPEED_PINCTRL_FUNC(MDIO1),
+ ASPEED_PINCTRL_FUNC(MDIO2),
+ ASPEED_PINCTRL_FUNC(OSCCLK),
+ ASPEED_PINCTRL_FUNC(PEWAKE),
+ ASPEED_PINCTRL_FUNC(PWM0),
+ ASPEED_PINCTRL_FUNC(PWM1),
+ ASPEED_PINCTRL_FUNC(PWM2),
+ ASPEED_PINCTRL_FUNC(PWM3),
+ ASPEED_PINCTRL_FUNC(PWM4),
+ ASPEED_PINCTRL_FUNC(PWM5),
+ ASPEED_PINCTRL_FUNC(PWM6),
+ ASPEED_PINCTRL_FUNC(PWM7),
+ ASPEED_PINCTRL_FUNC(RGMII1),
+ ASPEED_PINCTRL_FUNC(RGMII2),
+ ASPEED_PINCTRL_FUNC(RMII1),
+ ASPEED_PINCTRL_FUNC(RMII2),
+ ASPEED_PINCTRL_FUNC(SD1),
+ ASPEED_PINCTRL_FUNC(SPI1),
+ ASPEED_PINCTRL_FUNC(TIMER4),
+ ASPEED_PINCTRL_FUNC(TIMER5),
+ ASPEED_PINCTRL_FUNC(TIMER6),
+ ASPEED_PINCTRL_FUNC(TIMER7),
+ ASPEED_PINCTRL_FUNC(TIMER8),
+};
+
+static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
+ .pins = aspeed_g5_pins,
+ .npins = ARRAY_SIZE(aspeed_g5_pins),
+ .groups = aspeed_g5_groups,
+ .ngroups = ARRAY_SIZE(aspeed_g5_groups),
+ .functions = aspeed_g5_functions,
+ .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
+};
+
+static struct pinmux_ops aspeed_g5_pinmux_ops = {
+ .get_functions_count = aspeed_pinmux_get_fn_count,
+ .get_function_name = aspeed_pinmux_get_fn_name,
+ .get_function_groups = aspeed_pinmux_get_fn_groups,
+ .set_mux = aspeed_pinmux_set_mux,
+ .gpio_request_enable = aspeed_gpio_request_enable,
+ .strict = true,
+};
+
+static struct pinctrl_ops aspeed_g5_pinctrl_ops = {
+ .get_groups_count = aspeed_pinctrl_get_groups_count,
+ .get_group_name = aspeed_pinctrl_get_group_name,
+ .get_group_pins = aspeed_pinctrl_get_group_pins,
+ .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
+ .name = "aspeed-g5-pinctrl",
+ .pins = aspeed_g5_pins,
+ .npins = ARRAY_SIZE(aspeed_g5_pins),
+ .pctlops = &aspeed_g5_pinctrl_ops,
+ .pmxops = &aspeed_g5_pinmux_ops,
+};
+
+static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
+ aspeed_g5_pins[i].number = i;
+
+ return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
+ &aspeed_g5_pinctrl_data);
+}
+
+static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
+ { .compatible = "aspeed,ast2500-pinctrl", },
+ { .compatible = "aspeed,g5-pinctrl", },
+ { },
+};
+
+static struct platform_driver aspeed_g5_pinctrl_driver = {
+ .probe = aspeed_g5_pinctrl_probe,
+ .driver = {
+ .name = "aspeed-g5-pinctrl",
+ .of_match_table = aspeed_g5_pinctrl_of_match,
+ },
+};
+
+static int aspeed_g5_pinctrl_init(void)
+{
+ return platform_driver_register(&aspeed_g5_pinctrl_driver);
+}
+
+arch_initcall(aspeed_g5_pinctrl_init);
--
2.9.3.1.g0db844e
[toc] | [prev] | [next] | [standalone]
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-09-07 17:00 +0200 |
| Subject | Re: [PATCH v3 7/8] pinctrl: Add pinctrl-aspeed-g5 driver |
| Message-ID | <seMut-13P-15@gated-at.bofh.it> |
| In reply to | #1472282 |
2016-08-30 9:54 GMT+02:00 Andrew Jeffery <andrew@aj.id.au>: > A small subset of pins and functions are exposed. The selection of pins > and functions is driven by the development of OpenBMC[1] on the > AST2500 SoC, particularly around booting the IBM Witherspoon platform. > > [1] https://github.com/openbmc/docs > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Reviewed-by: Joel Stanley <joel@jms.id.au> Patch applied. Yours, Linus Walleij
[toc] | [prev] | [next] | [standalone]
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-08-30 10:00 +0200 |
| Subject | [PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings |
| Message-ID | <sbM7D-1Ul-11@gated-at.bofh.it> |
| In reply to | #1472280 |
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index a306795a7450..b9d5a9d4eee6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1027,6 +1027,7 @@ S: Maintained F: arch/arm/mach-aspeed/ F: arch/arm/boot/dts/aspeed-* F: drivers/*/*aspeed* +F: Documentation/devicetree/bindings/*/*aspeed* ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT M: Nicolas Ferre <nicolas.ferre@atmel.com> -- 2.9.3.1.g0db844e
[toc] | [prev] | [next] | [standalone]
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-09-07 16:40 +0200 |
| Subject | Re: [PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings |
| Message-ID | <seMb7-WB-1@gated-at.bofh.it> |
| In reply to | #1472283 |
On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> I guess some device tree maintainer or SoC tree should merge this patch. If you think it is proper to apply in the pinctrl or gpio tree, tell me. Yours, Linus Walleij
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| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Date | 2016-09-07 16:50 +0200 |
| Subject | Re: [PATCH v3 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings |
| Message-ID | <seMkO-109-13@gated-at.bofh.it> |
| In reply to | #1478336 |
On Wednesday, September 7, 2016 4:37:15 PM CEST Linus Walleij wrote: > On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Acked-by: Joel Stanley <joel@jms.id.au> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > I guess some device tree maintainer or SoC tree should merge this patch. > If you think it is proper to apply in the pinctrl or gpio tree, tell me. > I think it's best to take this through arm-soc to avoid conflicts in case we add other lines too. Maybe add a global regex instead of a growing list of file names though. Arnd
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-08-30 10:00 +0200 |
| Subject | [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers |
| Message-ID | <sbM7D-1Ul-25@gated-at.bofh.it> |
| In reply to | #1472280 |
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
---
.../devicetree/bindings/gpio/gpio-aspeed.txt | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
new file mode 100644
index 000000000000..09f26cac18d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
@@ -0,0 +1,36 @@
+Aspeed GPIO controller Device Tree Bindings
+-------------------------------------------
+
+Required properties:
+- #gpio-cells : Should be two
+ - First cell is the GPIO line number
+ - Second cell is used to specify optional
+ parameters (unused)
+
+- compatible : Either "aspeed,ast2400-gpio" or "aspeed,ast2500-gpio"
+
+- reg : Address and length of the register set for the device
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupts : Interrupt specifier (see interrupt bindings for
+ details)
+- interrupt-controller : Mark the GPIO controller as an interrupt-controller
+
+Optional properties:
+
+- interrupt-parent : The parent interrupt controller, optional if inherited
+
+The gpio and interrupt properties are further described in their respective
+bindings documentation:
+
+- Documentation/devicetree/bindings/gpio/gpio.txt
+- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+ Example:
+ gpio@1e780000 {
+ #gpio-cells = <2>;
+ compatible = "aspeed,ast2400-gpio";
+ gpio-controller;
+ interrupts = <20>;
+ reg = <0x1e780000 0x1000>;
+ interrupt-controller;
+ };
--
2.9.3.1.g0db844e
[toc] | [prev] | [next] | [standalone]
| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-09-02 17:10 +0200 |
| Subject | Re: [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers |
| Message-ID | <scYgq-13o-25@gated-at.bofh.it> |
| In reply to | #1472287 |
On Tue, Aug 30, 2016 at 05:24:23PM +0930, Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Acked-by: Joel Stanley <joel@jms.id.au>
> ---
> .../devicetree/bindings/gpio/gpio-aspeed.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
Acked-by: Rob Herring <robh@kernel.org>
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
> new file mode 100644
> index 000000000000..09f26cac18d1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
> @@ -0,0 +1,36 @@
> +Aspeed GPIO controller Device Tree Bindings
> +-------------------------------------------
> +
> +Required properties:
> +- #gpio-cells : Should be two
> + - First cell is the GPIO line number
> + - Second cell is used to specify optional
> + parameters (unused)
> +
> +- compatible : Either "aspeed,ast2400-gpio" or "aspeed,ast2500-gpio"
I'd prefer this be listed first if you respin this.
> +
> +- reg : Address and length of the register set for the device
> +- gpio-controller : Marks the device node as a GPIO controller.
> +- interrupts : Interrupt specifier (see interrupt bindings for
> + details)
> +- interrupt-controller : Mark the GPIO controller as an interrupt-controller
> +
> +Optional properties:
> +
> +- interrupt-parent : The parent interrupt controller, optional if inherited
> +
> +The gpio and interrupt properties are further described in their respective
> +bindings documentation:
> +
> +- Documentation/devicetree/bindings/gpio/gpio.txt
> +- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
> +
> + Example:
> + gpio@1e780000 {
> + #gpio-cells = <2>;
> + compatible = "aspeed,ast2400-gpio";
> + gpio-controller;
> + interrupts = <20>;
> + reg = <0x1e780000 0x1000>;
> + interrupt-controller;
> + };
> --
> 2.9.3.1.g0db844e
>
[toc] | [prev] | [next] | [standalone]
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-09-07 16:50 +0200 |
| Subject | Re: [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers |
| Message-ID | <seMkN-109-11@gated-at.bofh.it> |
| In reply to | #1472287 |
On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Acked-by: Joel Stanley <joel@jms.id.au> Patch applied to the GPIO tree with Rob's ACK and moved the compatible to the first line in the process. Yours, Linus Walleij
[toc] | [prev] | [next] | [standalone]
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-09-08 03:20 +0200 |
| Subject | Re: [PATCH v3 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers |
| Message-ID | <seWau-7zT-7@gated-at.bofh.it> |
| In reply to | #1478348 |
[Multipart message — attachments visible in raw view] — view raw
On Wed, 2016-09-07 at 16:43 +0200, Linus Walleij wrote: > On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Acked-by: Joel Stanley <joel@jms.id.au> > Patch applied to the GPIO tree with Rob's ACK and moved the compatible > to the first line in the process. Thanks for applying the fixup. Andrew
[toc] | [prev] | [next] | [standalone]
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-08-30 10:00 +0200 |
| Subject | [PATCH v3 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers |
| Message-ID | <sbM7D-1Ul-27@gated-at.bofh.it> |
| In reply to | #1472280 |
Outline expectations on the pin controller's relationship with the
System Control Unit (SCU) IP through syscon, and document the compatible
strings for 4th and 5th generation Aspeed SoC pin controllers.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Joel Stanley <joel@jms.id.au>
---
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
new file mode 100644
index 000000000000..5e60ad18f147
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -0,0 +1,65 @@
+Aspeed Pin Controllers
+----------------------
+
+The Aspeed SoCs vary in functionality inside a generation but have a common mux
+device register layout.
+
+Required properties:
+- compatible : Should be any one of the following:
+ "aspeed,ast2400-pinctrl"
+ "aspeed,g4-pinctrl"
+ "aspeed,ast2500-pinctrl"
+ "aspeed,g5-pinctrl"
+
+The pin controller node should be a child of a syscon node with the required
+property:
+- compatible: "syscon", "simple-mfd"
+
+Refer to the the bindings described in
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Subnode Format
+--------------
+
+The required properties of child nodes are (as defined in pinctrl-bindings):
+- function
+- groups
+
+Each function has only one associated pin group. Each group is named by its
+function. The following values for the function and groups properties are
+supported:
+
+aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
+
+ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10
+I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1
+MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3
+NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16
+ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30
+VPO12 VPO24
+
+aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
+
+GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
+I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
+RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
+
+Examples:
+
+syscon: scu@1e6e2000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g4-pinctrl";
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+ };
+};
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
--
2.9.3.1.g0db844e
[toc] | [prev] | [next] | [standalone]
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-09-07 16:50 +0200 |
| Subject | Re: [PATCH v3 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers |
| Message-ID | <seMkO-109-17@gated-at.bofh.it> |
| In reply to | #1472288 |
On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > Outline expectations on the pin controller's relationship with the > System Control Unit (SCU) IP through syscon, and document the compatible > strings for 4th and 5th generation Aspeed SoC pin controllers. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Acked-by: Rob Herring <robh@kernel.org> > Acked-by: Joel Stanley <joel@jms.id.au> Patch applied to the pinctrl tree. Yours, Linus Walleij
[toc] | [prev] | [next] | [standalone]
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-08-30 10:00 +0200 |
| Subject | [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units |
| Message-ID | <sbM7E-1Ul-45@gated-at.bofh.it> |
| In reply to | #1472280 |
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Joel Stanley <joel@jms.id.au>
---
Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-scu.txt
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
new file mode 100644
index 000000000000..4fc5b83726d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
@@ -0,0 +1,18 @@
+The Aspeed System Control Unit manages the global behaviour of the SoC,
+configuring elements such as clocks, pinmux, and reset.
+
+Required properties:
+- compatible: One of:
+ "aspeed,ast2400-scu", "syscon", "simple-mfd"
+ "aspeed,g4-scu", "syscon", "simple-mfd"
+ "aspeed,ast2500-scu", "syscon", "simple-mfd"
+ "aspeed,g5-scu", "syscon", "simple-mfd"
+
+- reg: contains the offset and length of the SCU memory region
+
+Example:
+
+syscon: syscon@1e6e2000 {
+ compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+};
--
2.9.3.1.g0db844e
[toc] | [prev] | [next] | [standalone]
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-09-07 16:40 +0200 |
| Subject | Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units |
| Message-ID | <seMb8-WB-25@gated-at.bofh.it> |
| In reply to | #1472295 |
On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Acked-by: Rob Herring <robh@kernel.org> > Acked-by: Joel Stanley <joel@jms.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> I guess the MFD maintainer (Lee Jones) should merge this? Why is he not on CC? Yours, Linus Walleij
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-09-07 18:30 +0200 |
| Subject | Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units |
| Message-ID | <seNTA-25W-25@gated-at.bofh.it> |
| In reply to | #1478342 |
On Wed, 07 Sep 2016, Linus Walleij wrote: > On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Acked-by: Rob Herring <robh@kernel.org> > > Acked-by: Joel Stanley <joel@jms.id.au> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > I guess the MFD maintainer (Lee Jones) should merge this? > > Why is he not on CC? Thanks Linus. Yes, please resend, so I can take it in. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-09-08 03:10 +0200 |
| Subject | Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units |
| Message-ID | <seW0O-7wI-9@gated-at.bofh.it> |
| In reply to | #1478473 |
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On Wed, 2016-09-07 at 17:30 +0100, Lee Jones wrote: > On Wed, 07 Sep 2016, Linus Walleij wrote: > > > > > On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > Acked-by: Rob Herring <robh@kernel.org> > > > Acked-by: Joel Stanley <joel@jms.id.au> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > > > I guess the MFD maintainer (Lee Jones) should merge this? > > > > Why is he not on CC? > Thanks Linus. > > Yes, please resend, so I can take it in. > Will do. Cheers, Andrew
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-09-08 03:10 +0200 |
| Subject | Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units |
| Message-ID | <seW0N-7wI-1@gated-at.bofh.it> |
| In reply to | #1478342 |
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On Wed, 2016-09-07 at 16:38 +0200, Linus Walleij wrote: > On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Acked-by: Rob Herring <robh@kernel.org> > > Acked-by: Joel Stanley <joel@jms.id.au> > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > I guess the MFD maintainer (Lee Jones) should merge this? > > Why is he not on CC? I used get_maintainer.pl on the series to construct the CC, but Lee wasn't listed in the output. I'll poke further at MAINTAINERs in the future to make sure I have coverage for affected subsystems. Andrew > > Yours, > Linus Walleij
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-09-08 09:10 +0200 |
| Subject | Re: [PATCH v3 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units |
| Message-ID | <sf1Dc-2F3-35@gated-at.bofh.it> |
| In reply to | #1478713 |
On Thu, 08 Sep 2016, Andrew Jeffery wrote: > On Wed, 2016-09-07 at 16:38 +0200, Linus Walleij wrote: > > On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > Acked-by: Rob Herring <robh@kernel.org> > > > Acked-by: Joel Stanley <joel@jms.id.au> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > > > I guess the MFD maintainer (Lee Jones) should merge this? > > > > Why is he not on CC? > > I used get_maintainer.pl on the series to construct the CC, but Lee > wasn't listed in the output. I'll poke further at MAINTAINERs in the > future to make sure I have coverage for affected subsystems. Good point. Will fix. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-09-07 17:00 +0200 |
| Subject | Re: [PATCH v3 5/8] pinctrl: Add core support for Aspeed SoCs |
| Message-ID | <seMuu-13P-41@gated-at.bofh.it> |
| In reply to | #1472280 |
On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > The Aspeed SoCs typically provide more than 200 pins for GPIO and other > functions. The signal enabled on a pin is determined on a priority > basis, where a given pin can provide a number of different signal types. > > In addition to the priority levels, the Aspeed pin controllers describe > the signal active on a pin by compound logical expressions involving > multiple operators, registers and bits. Some difficulty arises as a > pin's function bit masks for each priority level are frequently not the > same (i.e. we cannot just flip a bit to change from a high to low > priority signal), or even in the same register(s). Some configuration > bits affect multiple pins, while in other cases the signals for a bus > must each be enabled individually. > > Together, these features give rise to some complexity in the > implementation. A more complete description of the complexities is > provided in the associated header file. > > The patch doesn't implement pinctrl/pinmux/pinconf for any particular > Aspeed SoC, rather it adds the framework for defining pinmux > configurations. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Reviewed-by: Joel Stanley <joel@jms.id.au> Patch applied! It's not getting better than this through iteration, it is better to get the system up and develop inside the mainline tree from now on. > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1027,6 +1027,7 @@ S: Maintained > F: arch/arm/mach-aspeed/ > F: arch/arm/boot/dts/aspeed-* > F: drivers/*/*aspeed* > +F: drivers/pinctrl/aspeed/ > F: Documentation/devicetree/bindings/*/*aspeed* I dropped this hunk of the patch, because: (A) I didn't merge the glob patch and (B) the glob covers this driver too, it is a tautology/truism Yours, Linus Walleij
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| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-09-08 06:00 +0200 |
| Subject | Re: [PATCH v3 5/8] pinctrl: Add core support for Aspeed SoCs |
| Message-ID | <seYFj-AR-1@gated-at.bofh.it> |
| In reply to | #1478370 |
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On Wed, 2016-09-07 at 16:50 +0200, Linus Walleij wrote:
> On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> >
> > The Aspeed SoCs typically provide more than 200 pins for GPIO and other
> > functions. The signal enabled on a pin is determined on a priority
> > basis, where a given pin can provide a number of different signal types.
> >
> > In addition to the priority levels, the Aspeed pin controllers describe
> > the signal active on a pin by compound logical expressions involving
> > multiple operators, registers and bits. Some difficulty arises as a
> > pin's function bit masks for each priority level are frequently not the
> > same (i.e. we cannot just flip a bit to change from a high to low
> > priority signal), or even in the same register(s). Some configuration
> > bits affect multiple pins, while in other cases the signals for a bus
> > must each be enabled individually.
> >
> > Together, these features give rise to some complexity in the
> > implementation. A more complete description of the complexities is
> > provided in the associated header file.
> >
> > The patch doesn't implement pinctrl/pinmux/pinconf for any particular
> > Aspeed SoC, rather it adds the framework for defining pinmux
> > configurations.
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
> Patch applied! It's not getting better than this through iteration, it is better
> to get the system up and develop inside the mainline tree from now on.
>
> >
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1027,6 +1027,7 @@ S: Maintained
> > F: arch/arm/mach-aspeed/
> > F: arch/arm/boot/dts/aspeed-*
> > F: drivers/*/*aspeed*
> > +F: drivers/pinctrl/aspeed/
> > F: Documentation/devicetree/bindings/*/*aspeed*
> I dropped this hunk of the patch, because:
>
> (A) I didn't merge the glob patch and
Okay
> (B) the glob covers this driver too, it is a tautology/truism
So experimenting with this my results don't agree - without the hunk
get_maintainer.pl falls back to git and s-o-bs to pick up the Aspeed
maintainer:
With the hunk:
$ ./scripts/get_maintainer.pl drivers/pinctrl/aspeed/pinctrl-aspeed.c
Joel Stanley < joel@jms.id.au > (maintainer:ARM/ASPEED MACHINE SUPPORT)
Linus Walleij < linus.walleij@linaro.org > (maintainer:PIN CONTROL SUBSYSTEM)
linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM)
Without the hunk:
$ ./scripts/get_maintainer.pl drivers/pinctrl/aspeed/pinctrl-aspeed.c
Linus Walleij < linus.walleij@linaro.org > (maintainer:PIN CONTROL SUBSYSTEM)
Joel Stanley < joel@jms.id.au > (commit_signer:1/1=100%)
Andrew Jeffery < andrew@aj.id.au > (commit_signer:1/1=100%,authored:1/1=100%,added_lines:498/498=100%)
linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM)
linux-kernel@vger.kernel.org (open list)
So removing git as a fallback Joel isn't listed as a relevant
maintainer despite the glob:
$ ./scripts/get_maintainer.pl --no-git-fallback drivers/pinctrl/aspeed/pinctrl-aspeed.c
Linus Walleij < linus.walleij@linaro.org > (maintainer:PIN CONTROL SUBSYSTEM)
linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM)
linux-kernel@vger.kernel.org (open list)
I expect it's the case that the globbing doesn't match directories like
the hunk in question does with its trailing '/'. However, given we will
likely do something different in light of Arnd's suggestion it probably
doesn't matter.
Cheers,
Andrew
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