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[PATCH 00/22] Openrisc patchees from backlog for 4.11

Started by	Stafford Horne <shorne@gmail.com>
First post	2017-01-15 00:10 +0100
Last post	2017-01-16 13:00 +0100
Articles	20 on this page of 22 — 3 participants

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  [PATCH 00/22] Openrisc patchees from backlog for 4.11 Stafford Horne <shorne@gmail.com> - 2017-01-15 00:10 +0100
    [PATCH 19/22] scripts/checkstack.pl: Add openrisc support Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 16/22] openrisc: Add optimized memcpy routine Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 12/22] openrisc: remove unnecessary stddef.h include Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 21/22] openrisc: entry: Fix delay slot detection Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 14/22] openrisc: Initial support for the idle state Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 15/22] openrisc: Add optimized memset Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 10/22] openrisc: add spinlock implementation Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 11/22] openrisc: add futex_atomic_* implementations Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 03/22] openrisc: tlb miss handler optimizations Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 17/22] openrisc: Add .gitignore Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 13/22] openrisc: Fix the bitmask for the unit present register Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 22/22] openrisc: head: Move init strings to rodata section Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 07/22] openrisc: add atomic bitops Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
      Re: [PATCH 07/22] openrisc: add atomic bitops kbuild test robot <lkp@intel.com> - 2017-01-15 06:40 +0100
        Re: [PATCH 07/22] openrisc: add atomic bitops Stafford Horne <shorne@gmail.com> - 2017-01-15 09:30 +0100
    [PATCH 09/22] openrisc: add optimized atomic operations Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 18/22] MAINTAINERS: Add the openrisc official repository Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    [PATCH 20/22] openrisc: entry: Whitespace and comment cleanups Stafford Horne <shorne@gmail.com> - 2017-01-15 00:20 +0100
    Re: [PATCH 00/22] Openrisc patchees from backlog for 4.11 Guenter Roeck <linux@roeck-us.net> - 2017-01-15 06:20 +0100
      Re: [PATCH 00/22] Openrisc patchees from backlog for 4.11 Stafford Horne <shorne@gmail.com> - 2017-01-15 09:40 +0100
      Re: [PATCH 00/22] Openrisc patchees from backlog for 4.11 Stafford Horne <shorne@gmail.com> - 2017-01-16 13:00 +0100

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#1559098 — [PATCH 00/22] Openrisc patchees from backlog for 4.11

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:10 +0100
Subject	[PATCH 00/22] Openrisc patchees from backlog for 4.11
Message-ID	<sZFCq-3xP-15@gated-at.bofh.it>

Hi All,

This is another set of patches which I have been pulling out of the
openrisc backlogs. Its a bit of a process since I need to cleanup commit
messages, review and test the patches.

The interesting things here are:
 - optimized memset and memcpy routines, ~20% boot time saving
 - support for cpu idling
 - adding support for l.swa and l.lwa atomic operations (in spec from 2014)
 - use atomics to implement: bitops, cmpxchg, futex, spinlocks
 - the atomics are in preparation for SMP support

Testing:
I have used the kselftests to validate the changes especially the futex
operations with the futex test. Other atomic operations are common so no
explicit testing.

Note for testers:
The l.swa and l.lwa emulation is broken in qemu openrisc port. I have sent
patches [1] to qemu-devel to fix the qemu issues.

 [1] lists.nongnu.org/archive/html/qemu-devel/2017-01/msg02764.html

Jonas Bonn (1):
  openrisc: use SPARSE_IRQ

Olof Kindgren (1):
  openrisc: Add optimized memset

Sebastian Macke (2):
  openrisc: Fix the bitmask for the unit present register
  openrisc: Initial support for the idle state

Stafford Horne (7):
  openrisc: Add optimized memcpy routine
  openrisc: Add .gitignore
  MAINTAINERS: Add the openrisc official repository
  scripts/checkstack.pl: Add openrisc support
  openrisc: entry: Whitespace and comment cleanups
  openrisc: entry: Fix delay slot detection
  openrisc: head: Move init strings to rodata section

Stefan Kristiansson (11):
  openrisc: add cache way information to cpuinfo
  openrisc: tlb miss handler optimizations
  openrisc: head: use THREAD_SIZE instead of magic constant
  openrisc: head: refactor out tlb flush into it's own function
  openrisc: add l.lwa/l.swa emulation
  openrisc: add atomic bitops
  openrisc: add cmpxchg and xchg implementations
  openrisc: add optimized atomic operations
  openrisc: add spinlock implementation
  openrisc: add futex_atomic_* implementations
  openrisc: remove unnecessary stddef.h include

 MAINTAINERS                                |   1 +
 arch/openrisc/Kconfig                      |   1 +
 arch/openrisc/TODO.openrisc                |   1 -
 arch/openrisc/include/asm/Kbuild           |   5 +-
 arch/openrisc/include/asm/atomic.h         |  53 +++++++
 arch/openrisc/include/asm/bitops.h         |   2 +-
 arch/openrisc/include/asm/bitops/atomic.h  | 103 +++++++++++++
 arch/openrisc/include/asm/cmpxchg.h        |  82 ++++++++++
 arch/openrisc/include/asm/cpuinfo.h        |   2 +
 arch/openrisc/include/asm/futex.h          | 135 +++++++++++++++++
 arch/openrisc/include/asm/spinlock.h       | 232 ++++++++++++++++++++++++++++-
 arch/openrisc/include/asm/spinlock_types.h |  28 ++++
 arch/openrisc/include/asm/spr_defs.h       |   4 +-
 arch/openrisc/include/asm/string.h         |  10 ++
 arch/openrisc/kernel/.gitignore            |   1 +
 arch/openrisc/kernel/entry.S               |  60 +++++---
 arch/openrisc/kernel/head.S                | 195 +++++++++---------------
 arch/openrisc/kernel/or32_ksyms.c          |   1 +
 arch/openrisc/kernel/process.c             |  17 +++
 arch/openrisc/kernel/ptrace.c              |   1 -
 arch/openrisc/kernel/setup.c               |  67 +++++----
 arch/openrisc/kernel/traps.c               | 183 +++++++++++++++++++++++
 arch/openrisc/lib/Makefile                 |   2 +-
 arch/openrisc/lib/memcpy.c                 | 124 +++++++++++++++
 arch/openrisc/lib/memset.S                 |  98 ++++++++++++
 scripts/checkstack.pl                      |   3 +
 26 files changed, 1224 insertions(+), 187 deletions(-)
 create mode 100644 arch/openrisc/include/asm/atomic.h
 create mode 100644 arch/openrisc/include/asm/bitops/atomic.h
 create mode 100644 arch/openrisc/include/asm/cmpxchg.h
 create mode 100644 arch/openrisc/include/asm/futex.h
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h
 create mode 100644 arch/openrisc/include/asm/string.h
 create mode 100644 arch/openrisc/kernel/.gitignore
 create mode 100644 arch/openrisc/lib/memcpy.c
 create mode 100644 arch/openrisc/lib/memset.S

-- 
2.9.3

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#1559099 — [PATCH 19/22] scripts/checkstack.pl: Add openrisc support

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 19/22] scripts/checkstack.pl: Add openrisc support
Message-ID	<sZFM5-3B6-3@gated-at.bofh.it>
In reply to	#1559098

Openrisc stack pointer is managed by decrementing r1. Add regexes to
recognize this.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 scripts/checkstack.pl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/scripts/checkstack.pl b/scripts/checkstack.pl
index dd83978..eea5b78 100755
--- a/scripts/checkstack.pl
+++ b/scripts/checkstack.pl
@@ -106,6 +106,9 @@ my (@stack, $re, $dre, $x, $xs, $funcre);
 	} elsif ($arch eq 'sparc' || $arch eq 'sparc64') {
 		# f0019d10:       9d e3 bf 90     save  %sp, -112, %sp
 		$re = qr/.*save.*%sp, -(([0-9]{2}|[3-9])[0-9]{2}), %sp/o;
+	} elsif ($arch eq 'openrisc') {
+		# c000043c:       9c 21 fe f0     l.addi r1,r1,-272
+		$re = qr/.*l\.addi.*r1,r1,-(([0-9]{2}|[3-9])[0-9]{2})/o;
 	} else {
 		print("wrong or unknown architecture \"$arch\"\n");
 		exit
-- 
2.9.3

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#1559100 — [PATCH 16/22] openrisc: Add optimized memcpy routine

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 16/22] openrisc: Add optimized memcpy routine
Message-ID	<sZFM5-3B6-1@gated-at.bofh.it>
In reply to	#1559098

The generic memcpy routine provided in kernel does only byte copies.
Using word copies we can lower boot time and cycles spend in memcpy
quite significantly.

Booting on my de0 nano I see boot times go from 7.2 to 5.6 seconds.
The avg cycles in memcpy during boot go from 6467 to 1887.

I tested several algorithms (see code in previous patch mails)

The implementations I tested and avg cycles:
  - Word Copies + Loop Unrolls + Non Aligned    1882
  - Word Copies + Loop Unrolls                  1887
  - Word Copies                                 2441
  - Byte Copies + Loop Unrolls                  6467
  - Byte Copies                                 7600

In the end I ended up going with Word Copies + Loop Unrolls as it
provides best tradeoff between simplicity and boot speedups.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/TODO.openrisc        |   1 -
 arch/openrisc/include/asm/string.h |   3 +
 arch/openrisc/lib/Makefile         |   2 +-
 arch/openrisc/lib/memcpy.c         | 124 +++++++++++++++++++++++++++++++++++++
 4 files changed, 128 insertions(+), 2 deletions(-)
 create mode 100644 arch/openrisc/lib/memcpy.c

diff --git a/arch/openrisc/TODO.openrisc b/arch/openrisc/TODO.openrisc
index 0eb04c8..c43d4e1 100644
--- a/arch/openrisc/TODO.openrisc
+++ b/arch/openrisc/TODO.openrisc
@@ -10,4 +10,3 @@ that are due for investigation shortly, i.e. our TODO list:
    or1k and this change is slowly trickling through the stack.  For the time
    being, or32 is equivalent to or1k.
 
--- Implement optimized version of memcpy and memset
diff --git a/arch/openrisc/include/asm/string.h b/arch/openrisc/include/asm/string.h
index 33470d4..64939cc 100644
--- a/arch/openrisc/include/asm/string.h
+++ b/arch/openrisc/include/asm/string.h
@@ -4,4 +4,7 @@
 #define __HAVE_ARCH_MEMSET
 extern void *memset(void *s, int c, __kernel_size_t n);
 
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *dest, __const void *src, __kernel_size_t n);
+
 #endif /* __ASM_OPENRISC_STRING_H */
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index 67c583e..17d9d37 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -2,4 +2,4 @@
 # Makefile for or32 specific library files..
 #
 
-obj-y  = memset.o string.o delay.o
+obj-y	:= delay.o string.o memset.o memcpy.o
diff --git a/arch/openrisc/lib/memcpy.c b/arch/openrisc/lib/memcpy.c
new file mode 100644
index 0000000..4706f01
--- /dev/null
+++ b/arch/openrisc/lib/memcpy.c
@@ -0,0 +1,124 @@
+/*
+ * arch/openrisc/lib/memcpy.c
+ *
+ * Optimized memory copy routines for openrisc.  These are mostly copied
+ * from ohter sources but slightly entended based on ideas discuassed in
+ * #openrisc.
+ *
+ * The word unroll implementation is an extension to the arm byte
+ * unrolled implementation, but using word copies (if things are
+ * properly aligned)
+ *
+ * The great arm loop unroll algorithm can be found at:
+ *  arch/arm/boot/compressed/string.c
+ */
+
+#include <linux/export.h>
+
+#include <linux/string.h>
+
+#ifdef CONFIG_OR1200
+/*
+ * Do memcpy with word copies and loop unrolling. This gives the
+ * best performance on the OR1200 and MOR1KX archirectures
+ */
+void *memcpy(void *dest, __const void *src, __kernel_size_t n)
+{
+	int i = 0;
+	unsigned char *d, *s;
+	uint32_t *dest_w = (uint32_t *)dest, *src_w = (uint32_t *)src;
+
+	/* If both source and dest are word aligned copy words */
+	if (!((unsigned int)dest_w & 3) && !((unsigned int)src_w & 3)) {
+		/* Copy 32 bytes per loop */
+		for (i = n >> 5; i > 0; i--) {
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+		}
+
+		if (n & 1 << 4) {
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+		}
+
+		if (n & 1 << 3) {
+			*dest_w++ = *src_w++;
+			*dest_w++ = *src_w++;
+		}
+
+		if (n & 1 << 2)
+			*dest_w++ = *src_w++;
+
+		d = (unsigned char *)dest_w;
+		s = (unsigned char *)src_w;
+
+	} else {
+		d = (unsigned char *)dest_w;
+		s = (unsigned char *)src_w;
+
+		for (i = n >> 3; i > 0; i--) {
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+		}
+
+		if (n & 1 << 2) {
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+			*d++ = *s++;
+		}
+	}
+
+	if (n & 1 << 1) {
+		*d++ = *s++;
+		*d++ = *s++;
+	}
+
+	if (n & 1)
+		*d++ = *s++;
+
+	return dest;
+}
+#else
+/*
+ * Use word copies but no loop unrolling as we cannot assume there
+ * will be benefits on the archirecture
+ */
+void *memcpy(void *dest, __const void *src, __kernel_size_t n)
+{
+	unsigned char *d = (unsigned char *)dest, *s = (unsigned char *)src;
+	uint32_t *dest_w = (uint32_t *)dest, *src_w = (uint32_t *)src;
+
+	/* If both source and dest are word aligned copy words */
+	if (!((unsigned int)dest_w & 3) && !((unsigned int)src_w & 3)) {
+		for (; n >= 4; n -= 4)
+			*dest_w++ = *src_w++;
+	}
+
+	d = (unsigned char *)dest_w;
+	s = (unsigned char *)src_w;
+
+	/* For remaining or if not aligned, copy bytes */
+	for (; n >= 1; n -= 1)
+		*d++ = *s++;
+
+	return dest;
+
+}
+#endif
+
+EXPORT_SYMBOL(memcpy);
-- 
2.9.3

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#1559101 — [PATCH 12/22] openrisc: remove unnecessary stddef.h include

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 12/22] openrisc: remove unnecessary stddef.h include
Message-ID	<sZFM6-3B6-11@gated-at.bofh.it>
In reply to	#1559098

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

This causes the build to fail when building with the or1k-musl-linux-
toolchain and it is not needed.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/ptrace.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c
index 4f59fa4..2282888 100644
--- a/arch/openrisc/kernel/ptrace.c
+++ b/arch/openrisc/kernel/ptrace.c
@@ -16,7 +16,6 @@
  *      2 of the License, or (at your option) any later version.
  */
 
-#include <stddef.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/string.h>
-- 
2.9.3

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#1559102 — [PATCH 21/22] openrisc: entry: Fix delay slot detection

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 21/22] openrisc: entry: Fix delay slot detection
Message-ID	<sZFM5-3B6-5@gated-at.bofh.it>
In reply to	#1559098

Use execption SR stored in pt_regs for detection, the current SR is not
correct as the handler is running after return from exception.

Also, The code that checks for a delay slot uses a flag bitmask and then
wants to check if the result is not zero.  The test it implemented was
wrong.

Correct it by changing the test to check result against non zero.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/entry.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index daae2a4..bc65008 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -258,9 +258,9 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
 
 #else
 
-	l.mfspr r6,r0,SPR_SR               // SR
+	l.lwz   r6,PT_SR(r3)               // SR
 	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
-	l.sfeqi r6,0x1                     // exception happened in delay slot
+	l.sfne  r6,r0                      // exception happened in delay slot
 	l.bnf   7f
 	 l.lwz  r6,PT_PC(r3)               // address of an offending insn
 
-- 
2.9.3

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#1559103 — [PATCH 14/22] openrisc: Initial support for the idle state

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 14/22] openrisc: Initial support for the idle state
Message-ID	<sZFM5-3B6-7@gated-at.bofh.it>
In reply to	#1559098

From: Sebastian Macke <sebastian@macke.de>

This patch adds basic support for the idle state of the cpu.
The patch overrides the regular idle function, enables the interupts,
checks for the power management unit and enables the cpu doze mode
if available.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
[shorne@gmail.com: Fixed checkpatch, blankline after declarations]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/process.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/openrisc/kernel/process.c b/arch/openrisc/kernel/process.c
index c49350b..ffde77f 100644
--- a/arch/openrisc/kernel/process.c
+++ b/arch/openrisc/kernel/process.c
@@ -75,6 +75,20 @@ void machine_power_off(void)
 	__asm__("l.nop 1");
 }
 
+/*
+ * Send the doze signal to the cpu if available.
+ * Make sure, that all interrupts are enabled
+ */
+void arch_cpu_idle(void)
+{
+	unsigned long upr;
+
+	local_irq_enable();
+	upr = mfspr(SPR_UPR);
+	if (upr & SPR_UPR_PMP)
+		mtspr(SPR_PMR, mfspr(SPR_PMR) | SPR_PMR_DME);
+}
+
 void (*pm_power_off) (void) = machine_power_off;
 
 /*
-- 
2.9.3

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#1559104 — [PATCH 15/22] openrisc: Add optimized memset

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 15/22] openrisc: Add optimized memset
Message-ID	<sZFM5-3B6-9@gated-at.bofh.it>
In reply to	#1559098

From: Olof Kindgren <olof.kindgren@gmail.com>

This adds a hand-optimized assembler version of memset and sets
__HAVE_ARCH_MEMSET to use this version instead of the generic C
routine

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/string.h |  7 +++
 arch/openrisc/kernel/or32_ksyms.c  |  1 +
 arch/openrisc/lib/Makefile         |  2 +-
 arch/openrisc/lib/memset.S         | 98 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 107 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/string.h
 create mode 100644 arch/openrisc/lib/memset.S

diff --git a/arch/openrisc/include/asm/string.h b/arch/openrisc/include/asm/string.h
new file mode 100644
index 0000000..33470d4
--- /dev/null
+++ b/arch/openrisc/include/asm/string.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_OPENRISC_STRING_H
+#define __ASM_OPENRISC_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *s, int c, __kernel_size_t n);
+
+#endif /* __ASM_OPENRISC_STRING_H */
diff --git a/arch/openrisc/kernel/or32_ksyms.c b/arch/openrisc/kernel/or32_ksyms.c
index 86e31cf..5c4695d 100644
--- a/arch/openrisc/kernel/or32_ksyms.c
+++ b/arch/openrisc/kernel/or32_ksyms.c
@@ -44,3 +44,4 @@ DECLARE_EXPORT(__ashldi3);
 DECLARE_EXPORT(__lshrdi3);
 
 EXPORT_SYMBOL(__copy_tofrom_user);
+EXPORT_SYMBOL(memset);
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index 966f65d..67c583e 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -2,4 +2,4 @@
 # Makefile for or32 specific library files..
 #
 
-obj-y  = string.o delay.o
+obj-y  = memset.o string.o delay.o
diff --git a/arch/openrisc/lib/memset.S b/arch/openrisc/lib/memset.S
new file mode 100644
index 0000000..92cc2ea
--- /dev/null
+++ b/arch/openrisc/lib/memset.S
@@ -0,0 +1,98 @@
+/*
+ * OpenRISC memset.S
+ *
+ * Hand-optimized assembler version of memset for OpenRISC.
+ * Algorithm inspired by several other arch-specific memset routines
+ * in the kernel tree
+ *
+ * Copyright (C) 2015 Olof Kindgren <olof.kindgren@gmail.com>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+	.global memset
+	.type	memset, @function
+memset:
+	/* arguments:
+	 * r3 = *s
+	 * r4 = c
+	 * r5 = n
+	 * r13, r15, r17, r19 used as temp regs
+	*/
+
+	/* Exit if n == 0 */
+	l.sfeqi		r5, 0
+	l.bf		4f
+
+	/* Truncate c to char */
+	l.andi  	r13, r4, 0xff
+
+	/* Skip word extension if c is 0 */
+	l.sfeqi		r13, 0
+	l.bf		1f
+	/* Check for at least two whole words (8 bytes) */
+	 l.sfleui	r5, 7
+
+	/* Extend char c to 32-bit word cccc in r13 */
+	l.slli		r15, r13, 16  // r13 = 000c, r15 = 0c00
+	l.or		r13, r13, r15 // r13 = 0c0c, r15 = 0c00
+	l.slli		r15, r13, 8   // r13 = 0c0c, r15 = c0c0
+	l.or		r13, r13, r15 // r13 = cccc, r15 = c0c0
+
+1:	l.addi		r19, r3, 0 // Set r19 = src
+	/* Jump to byte copy loop if less than two words */
+	l.bf		3f
+	 l.or		r17, r5, r0 // Set r17 = n
+
+	/* Mask out two LSBs to check alignment */
+	l.andi		r15, r3, 0x3
+
+	/* lsb == 00, jump to word copy loop */
+	l.sfeqi		r15, 0
+	l.bf		2f
+	 l.addi		r19, r3, 0 // Set r19 = src
+
+	/* lsb == 01,10 or 11 */
+	l.sb		0(r3), r13   // *src = c
+	l.addi		r17, r17, -1 // Decrease n
+
+	l.sfeqi		r15, 3
+	l.bf		2f
+	 l.addi		r19, r3, 1  // src += 1
+
+	/* lsb == 01 or 10 */
+	l.sb		1(r3), r13   // *(src+1) = c
+	l.addi		r17, r17, -1 // Decrease n
+
+	l.sfeqi		r15, 2
+	l.bf		2f
+	 l.addi		r19, r3, 2  // src += 2
+
+	/* lsb == 01 */
+	l.sb		2(r3), r13   // *(src+2) = c
+	l.addi		r17, r17, -1 // Decrease n
+	l.addi		r19, r3, 3   // src += 3
+
+	/* Word copy loop */
+2:	l.sw		0(r19), r13  // *src = cccc
+	l.addi		r17, r17, -4 // Decrease n
+	l.sfgeui	r17, 4
+	l.bf		2b
+	 l.addi		r19, r19, 4  // Increase src
+
+	/* When n > 0, copy the remaining bytes, otherwise jump to exit */
+	l.sfeqi		r17, 0
+	l.bf		4f
+
+	/* Byte copy loop */
+3:	l.addi		r17, r17, -1 // Decrease n
+	l.sb		0(r19), r13  // *src = cccc
+	l.sfnei		r17, 0
+	l.bf		3b
+	 l.addi		r19, r19, 1  // Increase src
+
+4:	l.jr		r9
+	 l.ori		r11, r3, 0
-- 
2.9.3

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#1559105 — [PATCH 10/22] openrisc: add spinlock implementation

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 10/22] openrisc: add spinlock implementation
Message-ID	<sZFM6-3B6-17@gated-at.bofh.it>
In reply to	#1559098

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Heavily based on the ARM implementation, this adds
ticket spinlock support for OpenRISC.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: fix tabs vs space checkpatch warning]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/spinlock.h       | 232 ++++++++++++++++++++++++++++-
 arch/openrisc/include/asm/spinlock_types.h |  28 ++++
 2 files changed, 259 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h

diff --git a/arch/openrisc/include/asm/spinlock.h b/arch/openrisc/include/asm/spinlock.h
index fd00a3a..adf62a6 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -9,6 +9,9 @@
  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  * et al.
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ *
+ * Ticket spinlocks, based on the ARM implementation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,6 +22,233 @@
 #ifndef __ASM_OPENRISC_SPINLOCK_H
 #define __ASM_OPENRISC_SPINLOCK_H
 
-#error "or32 doesn't do SMP yet"
+#include <asm/spinlock_types.h>
+
+#define arch_spin_unlock_wait(lock) \
+	do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
+
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+
+static inline void arch_spin_lock(arch_spinlock_t *lock)
+{
+	u32 newval;
+	arch_spinlock_t lockval;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0, 0(%2)	\n"
+		"	l.add	%1, %0, %3	\n"
+		"	l.swa	0(%2), %1	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r" (lockval), "=&r" (newval)
+		: "r" (&lock->slock), "r" (1 << TICKET_SHIFT)
+		: "cc", "memory");
+
+	while (lockval.tickets.next != lockval.tickets.owner)
+		lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
+
+	smp_mb();
+}
+
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
+{
+	unsigned long contended, tmp;
+	u32 slock;
+
+	/* contended = (lock->tickets.owner != lock->tickets.next) */
+	__asm__ __volatile__(
+		"1:	l.lwa	%0, 0(%3)	\n"
+		"	l.srli	%1, %0, 16	\n"
+		"	l.andi	%2, %0, 0xffff	\n"
+		"	l.sfeq	%1, %2		\n"
+		"	l.bnf	1f		\n"
+		"	 l.ori	%1, r0, 1	\n"
+		"	l.add	%0, %0, %4	\n"
+		"	l.swa	0(%3), %0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.ori	%1, r0, 0	\n"
+		"1:				\n"
+		: "=&r" (slock), "=&r" (contended), "=&r" (tmp)
+		: "r" (&lock->slock), "r" (1 << TICKET_SHIFT)
+		: "cc", "memory");
+
+	if (!contended) {
+		smp_mb();
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
+{
+	smp_mb();
+	lock->tickets.owner++;
+}
+
+static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
+{
+	return lock.tickets.owner == lock.tickets.next;
+}
+
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+	return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));
+}
+
+static inline int arch_spin_is_contended(arch_spinlock_t *lock)
+{
+	struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
+
+	return (tickets.next - tickets.owner) > 1;
+}
+#define arch_spin_is_contended	arch_spin_is_contended
+
+/*
+ * RWLOCKS
+ *
+ *
+ * Write locks are easy - we just set bit 31.  When unlocking, we can
+ * just write zero since the lock is exclusively held.
+ */
+
+static inline void arch_write_lock(arch_rwlock_t *rw)
+{
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0, 0(%1)	\n"
+		"	l.sfeqi	%0, 0		\n"
+		"	l.bnf	1f		\n"
+		"	 l.nop			\n"
+		"	l.swa	0(%1), %2	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		"1:				\n"
+		: "=&r" (tmp)
+		: "r" (&rw->lock), "r" (0x80000000)
+		: "cc", "memory");
+
+	smp_mb();
+}
+
+static inline int arch_write_trylock(arch_rwlock_t *rw)
+{
+	unsigned long contended;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0, 0(%1)	\n"
+		"	l.sfeqi	%0, 0		\n"
+		"	l.bnf	1f		\n"
+		"	 l.nop			\n"
+		"	l.swa	 0(%1), %2	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		"1:				\n"
+		: "=&r" (contended)
+		: "r" (&rw->lock), "r" (0x80000000)
+		: "cc", "memory");
+
+	if (!contended) {
+		smp_mb();
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static inline void arch_write_unlock(arch_rwlock_t *rw)
+{
+	smp_mb();
+	rw->lock = 0;
+}
+
+/* write_can_lock - would write_trylock() succeed? */
+#define arch_write_can_lock(x)		(ACCESS_ONCE((x)->lock) == 0)
+
+/*
+ * Read locks are a bit more hairy:
+ *  - Exclusively load the lock value.
+ *  - Increment it.
+ *  - Store new lock value if positive, and we still own this location.
+ *    If the value is negative, we've already failed.
+ *  - If we failed to store the value, we want a negative result.
+ *  - If we failed, try again.
+ * Unlocking is similarly hairy.  We may have multiple read locks
+ * currently active.  However, we know we won't have any write
+ * locks.
+ */
+static inline void arch_read_lock(arch_rwlock_t *rw)
+{
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa		%0, 0(%1)	\n"
+		"	l.sfltsi	%0, -1		\n"
+		"	l.bf		1b		\n"
+		"	 l.addi		%0, %0, 1	\n"
+		"	l.swa		0(%1), %0	\n"
+		"	l.bnf		1b		\n"
+		"	 l.nop				\n"
+		: "=&r" (tmp)
+		: "r" (&rw->lock)
+		: "cc", "memory");
+
+	smp_mb();
+}
+
+static inline void arch_read_unlock(arch_rwlock_t *rw)
+{
+	unsigned long tmp;
+
+	smp_mb();
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0, 0(%1)	\n"
+		"	l.addi	%0, %0, -1	\n"
+		"	l.swa	0(%1), %0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r" (tmp)
+		: "r" (&rw->lock)
+		: "cc", "memory");
+
+}
+
+static inline int arch_read_trylock(arch_rwlock_t *rw)
+{
+	unsigned long contended;
+
+	__asm__ __volatile__(
+		"1:	l.lwa		%0, 0(%1)	\n"
+		"	l.sfltsi	%0, -1		\n"
+		"	l.bf		1f		\n"
+		"	 l.addi		%0, %0, 1	\n"
+		"	l.swa		0(%1), %0	\n"
+		"	l.bnf		1b		\n"
+		"	 l.nop				\n"
+		"1:					\n"
+		: "=&r" (contended)
+		: "r" (&rw->lock)
+		: "cc", "memory");
+
+	/* If the lock is negative, then it is already held for write. */
+	if (contended < 0x80000000) {
+		smp_mb();
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/* read_can_lock - would read_trylock() succeed? */
+#define arch_read_can_lock(x)		(ACCESS_ONCE((x)->lock) < 0x80000000)
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock)	cpu_relax()
+#define arch_read_relax(lock)	cpu_relax()
+#define arch_write_relax(lock)	cpu_relax()
 
 #endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index 0000000..bc0de48
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_SPINLOCK_TYPES_H
+#define __ASM_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+#define TICKET_SHIFT	16
+
+typedef struct {
+	union {
+		u32 slock;
+		struct __raw_tickets {
+			u16 next;
+			u16 owner;
+		} tickets;
+	};
+} arch_spinlock_t;
+
+#define __ARCH_SPIN_LOCK_UNLOCKED	{ { 0 } }
+
+typedef struct {
+	u32 lock;
+} arch_rwlock_t;
+
+#define __ARCH_RW_LOCK_UNLOCKED		{ 0 }
+
+#endif
-- 
2.9.3

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#1559106 — [PATCH 11/22] openrisc: add futex_atomic_* implementations

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 11/22] openrisc: add futex_atomic_* implementations
Message-ID	<sZFM6-3B6-13@gated-at.bofh.it>
In reply to	#1559098

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Support for the futex_atomic_* operations by using the
load-link/store-conditional l.lwa/l.swa instructions.
Most openrisc cores provide these instructions now if not available,
emulation is provided.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by
Alan Cox https://lkml.org/lkml/2014/7/23/666]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/Kbuild  |   1 -
 arch/openrisc/include/asm/futex.h | 135 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/futex.h

diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 1cedd63..a669c14 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -20,7 +20,6 @@ generic-y += exec.h
 generic-y += fb.h
 generic-y += fcntl.h
 generic-y += ftrace.h
-generic-y += futex.h
 generic-y += hardirq.h
 generic-y += hw_irq.h
 generic-y += ioctl.h
diff --git a/arch/openrisc/include/asm/futex.h b/arch/openrisc/include/asm/futex.h
new file mode 100644
index 0000000..7780873
--- /dev/null
+++ b/arch/openrisc/include/asm/futex.h
@@ -0,0 +1,135 @@
+#ifndef __ASM_OPENRISC_FUTEX_H
+#define __ASM_OPENRISC_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
+({								\
+	__asm__ __volatile__ (					\
+		"1:	l.lwa	%0, %2			\n"	\
+			insn				"\n"	\
+		"2:	l.swa	%2, %1			\n"	\
+		"	l.bnf	1b			\n"	\
+		"	 l.ori	%1, r0, 0		\n"	\
+		"3:					\n"	\
+		".section .fixup,\"ax\"			\n"	\
+		"4:	l.j	3b			\n"	\
+		"	 l.addi	%1, r0, %3		\n"	\
+		".previous				\n"	\
+		".section __ex_table,\"a\"		\n"	\
+		".word	1b,4b,2b,4b			\n"	\
+		".previous				\n"	\
+		: "=&r" (oldval), "=&r" (ret), "+m" (*uaddr)	\
+		: "i" (-EFAULT), "r" (oparg)			\
+		: "cc", "memory"				\
+		);						\
+})
+
+static inline int
+futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
+{
+	int op = (encoded_op >> 28) & 7;
+	int cmp = (encoded_op >> 24) & 15;
+	int oparg = (encoded_op << 8) >> 20;
+	int cmparg = (encoded_op << 20) >> 20;
+	int oldval = 0, ret;
+
+	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+		oparg = 1 << oparg;
+
+	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+		return -EFAULT;
+
+	pagefault_disable();
+
+	switch (op) {
+	case FUTEX_OP_SET:
+		__futex_atomic_op("l.or %1,%4,%4", ret, oldval, uaddr, oparg);
+		break;
+	case FUTEX_OP_ADD:
+		__futex_atomic_op("l.add %1,%0,%4", ret, oldval, uaddr, oparg);
+		break;
+	case FUTEX_OP_OR:
+		__futex_atomic_op("l.or %1,%0,%4", ret, oldval, uaddr, oparg);
+		break;
+	case FUTEX_OP_ANDN:
+		__futex_atomic_op("l.and %1,%0,%4", ret, oldval, uaddr, ~oparg);
+		break;
+	case FUTEX_OP_XOR:
+		__futex_atomic_op("l.xor %1,%0,%4", ret, oldval, uaddr, oparg);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	pagefault_enable();
+
+	if (!ret) {
+		switch (cmp) {
+		case FUTEX_OP_CMP_EQ:
+			ret = (oldval == cmparg);
+			break;
+		case FUTEX_OP_CMP_NE:
+			ret = (oldval != cmparg);
+			break;
+		case FUTEX_OP_CMP_LT:
+			ret = (oldval < cmparg);
+			break;
+		case FUTEX_OP_CMP_GE:
+			ret = (oldval >= cmparg);
+			break;
+		case FUTEX_OP_CMP_LE:
+			ret = (oldval <= cmparg);
+			break;
+		case FUTEX_OP_CMP_GT:
+			ret = (oldval > cmparg);
+			break;
+		default:
+			ret = -ENOSYS;
+		}
+	}
+	return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+			      u32 oldval, u32 newval)
+{
+	int ret = 0;
+	u32 prev;
+
+	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+		return -EFAULT;
+
+	__asm__ __volatile__ (				\
+		"1:	l.lwa	%1, %2		\n"	\
+		"	l.sfeq	%1, %3		\n"	\
+		"	l.bnf	3f		\n"	\
+		"	 l.nop			\n"	\
+		"2:	l.swa	%2, %4		\n"	\
+		"	l.bnf	1b		\n"	\
+		"	 l.nop			\n"	\
+		"3:				\n"	\
+		".section .fixup,\"ax\"		\n"	\
+		"4:	l.j	3b		\n"	\
+		"	 l.addi	%0, r0, %5	\n"	\
+		".previous			\n"	\
+		".section __ex_table,\"a\"	\n"	\
+		".word	1b,4b,2b,4b		\n"	\
+		".previous			\n"	\
+		: "+r" (ret), "=&r" (prev), "+m" (*uaddr) \
+		: "r" (oldval), "r" (newval), "i" (-EFAULT) \
+		: "cc",	"memory"			\
+		);
+
+	*uval = prev;
+	return ret;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_OPENRISC_FUTEX_H */
-- 
2.9.3

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#1559107 — [PATCH 03/22] openrisc: tlb miss handler optimizations

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 03/22] openrisc: tlb miss handler optimizations
Message-ID	<sZFM6-3B6-29@gated-at.bofh.it>
In reply to	#1559098

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

By slightly reorganizing the code, the number of registers
used in the tlb miss handlers can be reduced by two,
thus removing the need to save them to memory.

Also, some dead and commented out code is removed.

No functional change.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/head.S | 141 +++++++++++++++-----------------------------
 1 file changed, 46 insertions(+), 95 deletions(-)

diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index f147933..2346c5b 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -971,8 +971,6 @@ ENTRY(dtlb_miss_handler)
 	EXCEPTION_STORE_GPR2
 	EXCEPTION_STORE_GPR3
 	EXCEPTION_STORE_GPR4
-	EXCEPTION_STORE_GPR5
-	EXCEPTION_STORE_GPR6
 	/*
 	 * get EA of the miss
 	 */
@@ -980,91 +978,70 @@ ENTRY(dtlb_miss_handler)
 	/*
 	 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
 	 */
-	GET_CURRENT_PGD(r3,r5)		// r3 is current_pgd, r5 is temp
+	GET_CURRENT_PGD(r3,r4)		// r3 is current_pgd, r4 is temp
 	l.srli	r4,r2,0x18		// >> PAGE_SHIFT + (PAGE_SHIFT - 2)
 	l.slli	r4,r4,0x2		// to get address << 2
-	l.add	r5,r4,r3		// r4 is pgd_index(daddr)
+	l.add	r3,r4,r3		// r4 is pgd_index(daddr)
 	/*
 	 * if (pmd_none(*pmd))
 	 *   goto pmd_none:
 	 */
-	tophys	(r4,r5)
+	tophys	(r4,r3)
 	l.lwz	r3,0x0(r4)		// get *pmd value
 	l.sfne	r3,r0
 	l.bnf	d_pmd_none
-	 l.andi	r3,r3,~PAGE_MASK //0x1fff		// ~PAGE_MASK
-	/*
-	 * if (pmd_bad(*pmd))
-	 *   pmd_clear(pmd)
-	 *   goto pmd_bad:
-	 */
-//	l.sfeq	r3,r0			// check *pmd value
-//	l.bf	d_pmd_good
-	l.addi	r3,r0,0xffffe000	// PAGE_MASK
-//	l.j	d_pmd_bad
-//	l.sw	0x0(r4),r0		// clear pmd
+	 l.addi	r3,r0,0xffffe000	// PAGE_MASK
+
 d_pmd_good:
 	/*
 	 * pte = *pte_offset(pmd, daddr);
 	 */
 	l.lwz	r4,0x0(r4)		// get **pmd value
 	l.and	r4,r4,r3		// & PAGE_MASK
-	l.srli	r5,r2,0xd		// >> PAGE_SHIFT, r2 == EEAR
-	l.andi	r3,r5,0x7ff		// (1UL << PAGE_SHIFT - 2) - 1
+	l.srli	r2,r2,0xd		// >> PAGE_SHIFT, r2 == EEAR
+	l.andi	r3,r2,0x7ff		// (1UL << PAGE_SHIFT - 2) - 1
 	l.slli	r3,r3,0x2		// to get address << 2
 	l.add	r3,r3,r4
-	l.lwz	r2,0x0(r3)		// this is pte at last
+	l.lwz	r3,0x0(r3)		// this is pte at last
 	/*
 	 * if (!pte_present(pte))
 	 */
-	l.andi	r4,r2,0x1
+	l.andi	r4,r3,0x1
 	l.sfne	r4,r0			// is pte present
 	l.bnf	d_pte_not_present
-	l.addi	r3,r0,0xffffe3fa	// PAGE_MASK | DTLB_UP_CONVERT_MASK
+	l.addi	r4,r0,0xffffe3fa	// PAGE_MASK | DTLB_UP_CONVERT_MASK
 	/*
 	 * fill DTLB TR register
 	 */
-	l.and	r4,r2,r3		// apply the mask
+	l.and	r4,r3,r4		// apply the mask
 	// Determine number of DMMU sets
-	l.mfspr r6, r0, SPR_DMMUCFGR
-	l.andi	r6, r6, SPR_DMMUCFGR_NTS
-	l.srli	r6, r6, SPR_DMMUCFGR_NTS_OFF
+	l.mfspr r2, r0, SPR_DMMUCFGR
+	l.andi	r2, r2, SPR_DMMUCFGR_NTS
+	l.srli	r2, r2, SPR_DMMUCFGR_NTS_OFF
 	l.ori	r3, r0, 0x1
-	l.sll	r3, r3, r6 	// r3 = number DMMU sets DMMUCFGR
-	l.addi	r6, r3, -1  	// r6 = nsets mask
-	l.and	r5, r5, r6	// calc offset:	 & (NUM_TLB_ENTRIES-1)
+	l.sll	r3, r3, r2 	// r3 = number DMMU sets DMMUCFGR
+	l.addi	r2, r3, -1  	// r2 = nsets mask
+	l.mfspr	r3, r0, SPR_EEAR_BASE
+	l.srli	r3, r3, 0xd	// >> PAGE_SHIFT
+	l.and	r2, r3, r2	// calc offset:	 & (NUM_TLB_ENTRIES-1)
 	                                                   //NUM_TLB_ENTRIES
-	l.mtspr	r5,r4,SPR_DTLBTR_BASE(0)
+	l.mtspr	r2,r4,SPR_DTLBTR_BASE(0)
 	/*
 	 * fill DTLB MR register
 	 */
-	l.mfspr	r2,r0,SPR_EEAR_BASE
-	l.addi	r3,r0,0xffffe000	// PAGE_MASK
-	l.and	r4,r2,r3		// apply PAGE_MASK to EA (__PHX__ do we really need this?)
-	l.ori	r4,r4,0x1		// set hardware valid bit: DTBL_MR entry
-	l.mtspr	r5,r4,SPR_DTLBMR_BASE(0)
+	l.slli	r3, r3, 0xd		/* << PAGE_SHIFT => EA & PAGE_MASK */
+	l.ori	r4,r3,0x1		// set hardware valid bit: DTBL_MR entry
+	l.mtspr	r2,r4,SPR_DTLBMR_BASE(0)
 
 	EXCEPTION_LOAD_GPR2
 	EXCEPTION_LOAD_GPR3
 	EXCEPTION_LOAD_GPR4
-	EXCEPTION_LOAD_GPR5
-	EXCEPTION_LOAD_GPR6
-	l.rfe
-d_pmd_bad:
-	l.nop	1
-	EXCEPTION_LOAD_GPR2
-	EXCEPTION_LOAD_GPR3
-	EXCEPTION_LOAD_GPR4
-	EXCEPTION_LOAD_GPR5
-	EXCEPTION_LOAD_GPR6
 	l.rfe
 d_pmd_none:
 d_pte_not_present:
 	EXCEPTION_LOAD_GPR2
 	EXCEPTION_LOAD_GPR3
 	EXCEPTION_LOAD_GPR4
-	EXCEPTION_LOAD_GPR5
-	EXCEPTION_LOAD_GPR6
 	EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
 
 /* ==============================================[ ITLB miss handler ]=== */
@@ -1072,8 +1049,6 @@ ENTRY(itlb_miss_handler)
 	EXCEPTION_STORE_GPR2
 	EXCEPTION_STORE_GPR3
 	EXCEPTION_STORE_GPR4
-	EXCEPTION_STORE_GPR5
-	EXCEPTION_STORE_GPR6
 	/*
 	 * get EA of the miss
 	 */
@@ -1083,30 +1058,19 @@ ENTRY(itlb_miss_handler)
 	 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
 	 *
 	 */
-	GET_CURRENT_PGD(r3,r5)		// r3 is current_pgd, r5 is temp
+	GET_CURRENT_PGD(r3,r4)		// r3 is current_pgd, r5 is temp
 	l.srli	r4,r2,0x18		// >> PAGE_SHIFT + (PAGE_SHIFT - 2)
 	l.slli	r4,r4,0x2		// to get address << 2
-	l.add	r5,r4,r3		// r4 is pgd_index(daddr)
+	l.add	r3,r4,r3		// r4 is pgd_index(daddr)
 	/*
 	 * if (pmd_none(*pmd))
 	 *   goto pmd_none:
 	 */
-	tophys	(r4,r5)
+	tophys	(r4,r3)
 	l.lwz	r3,0x0(r4)		// get *pmd value
 	l.sfne	r3,r0
 	l.bnf	i_pmd_none
-	l.andi	r3,r3,0x1fff		// ~PAGE_MASK
-	/*
-	 * if (pmd_bad(*pmd))
-	 *   pmd_clear(pmd)
-	 *   goto pmd_bad:
-	 */
-
-//	l.sfeq	r3,r0			// check *pmd value
-//	l.bf	i_pmd_good
-	l.addi	r3,r0,0xffffe000	// PAGE_MASK
-//	l.j	i_pmd_bad
-//	l.sw	0x0(r4),r0		// clear pmd
+	 l.addi	r3,r0,0xffffe000	// PAGE_MASK
 
 i_pmd_good:
 	/*
@@ -1115,35 +1079,36 @@ i_pmd_good:
 	 */
 	l.lwz	r4,0x0(r4)		// get **pmd value
 	l.and	r4,r4,r3		// & PAGE_MASK
-	l.srli	r5,r2,0xd		// >> PAGE_SHIFT, r2 == EEAR
-	l.andi	r3,r5,0x7ff		// (1UL << PAGE_SHIFT - 2) - 1
+	l.srli	r2,r2,0xd		// >> PAGE_SHIFT, r2 == EEAR
+	l.andi	r3,r2,0x7ff		// (1UL << PAGE_SHIFT - 2) - 1
 	l.slli	r3,r3,0x2		// to get address << 2
 	l.add	r3,r3,r4
-	l.lwz	r2,0x0(r3)		// this is pte at last
+	l.lwz	r3,0x0(r3)		// this is pte at last
 	/*
 	 * if (!pte_present(pte))
 	 *
 	 */
-	l.andi	r4,r2,0x1
+	l.andi	r4,r3,0x1
 	l.sfne	r4,r0			// is pte present
 	l.bnf	i_pte_not_present
-	l.addi	r3,r0,0xffffe03a	// PAGE_MASK | ITLB_UP_CONVERT_MASK
+	 l.addi	r4,r0,0xffffe03a	// PAGE_MASK | ITLB_UP_CONVERT_MASK
 	/*
 	 * fill ITLB TR register
 	 */
-	l.and	r4,r2,r3		// apply the mask
-	l.andi	r3,r2,0x7c0		// _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE |  _PAGE_URE | _PAGE_UWE
-//	l.andi	r3,r2,0x400		// _PAGE_EXEC
+	l.and	r4,r3,r4		// apply the mask
+	l.andi	r3,r3,0x7c0		// _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE |  _PAGE_URE | _PAGE_UWE
 	l.sfeq	r3,r0
 	l.bf	itlb_tr_fill //_workaround
 	// Determine number of IMMU sets
-	l.mfspr r6, r0, SPR_IMMUCFGR
-	l.andi	r6, r6, SPR_IMMUCFGR_NTS
-	l.srli	r6, r6, SPR_IMMUCFGR_NTS_OFF
+	l.mfspr r2, r0, SPR_IMMUCFGR
+	l.andi	r2, r2, SPR_IMMUCFGR_NTS
+	l.srli	r2, r2, SPR_IMMUCFGR_NTS_OFF
 	l.ori	r3, r0, 0x1
-	l.sll	r3, r3, r6 	// r3 = number IMMU sets IMMUCFGR
-	l.addi	r6, r3, -1  	// r6 = nsets mask
-	l.and	r5, r5, r6	// calc offset:	 & (NUM_TLB_ENTRIES-1)
+	l.sll	r3, r3, r2 	// r3 = number IMMU sets IMMUCFGR
+	l.addi	r2, r3, -1  	// r2 = nsets mask
+	l.mfspr	r3, r0, SPR_EEAR_BASE
+	l.srli	r3, r3, 0xd	// >> PAGE_SHIFT
+	l.and	r2, r3, r2	// calc offset:	 & (NUM_TLB_ENTRIES-1)
 
 /*
  * __PHX__ :: fixme
@@ -1155,38 +1120,24 @@ i_pmd_good:
 itlb_tr_fill_workaround:
 	l.ori	r4,r4,0xc0		// | (SPR_ITLBTR_UXE | ITLBTR_SXE)
 itlb_tr_fill:
-	l.mtspr	r5,r4,SPR_ITLBTR_BASE(0)
+	l.mtspr	r2,r4,SPR_ITLBTR_BASE(0)
 	/*
 	 * fill DTLB MR register
 	 */
-	l.mfspr	r2,r0,SPR_EEAR_BASE
-	l.addi	r3,r0,0xffffe000	// PAGE_MASK
-	l.and	r4,r2,r3		// apply PAGE_MASK to EA (__PHX__ do we really need this?)
-	l.ori	r4,r4,0x1		// set hardware valid bit: DTBL_MR entry
-	l.mtspr	r5,r4,SPR_ITLBMR_BASE(0)
+	l.slli	r3, r3, 0xd		/* << PAGE_SHIFT => EA & PAGE_MASK */
+	l.ori	r4,r3,0x1		// set hardware valid bit: ITBL_MR entry
+	l.mtspr	r2,r4,SPR_ITLBMR_BASE(0)
 
 	EXCEPTION_LOAD_GPR2
 	EXCEPTION_LOAD_GPR3
 	EXCEPTION_LOAD_GPR4
-	EXCEPTION_LOAD_GPR5
-	EXCEPTION_LOAD_GPR6
 	l.rfe
 
-i_pmd_bad:
-	l.nop	1
-	EXCEPTION_LOAD_GPR2
-	EXCEPTION_LOAD_GPR3
-	EXCEPTION_LOAD_GPR4
-	EXCEPTION_LOAD_GPR5
-	EXCEPTION_LOAD_GPR6
-	l.rfe
 i_pmd_none:
 i_pte_not_present:
 	EXCEPTION_LOAD_GPR2
 	EXCEPTION_LOAD_GPR3
 	EXCEPTION_LOAD_GPR4
-	EXCEPTION_LOAD_GPR5
-	EXCEPTION_LOAD_GPR6
 	EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
 
 /* ==============================================[ boot tlb handlers ]=== */
-- 
2.9.3

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#1559108 — [PATCH 17/22] openrisc: Add .gitignore

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 17/22] openrisc: Add .gitignore
Message-ID	<sZFM6-3B6-31@gated-at.bofh.it>
In reply to	#1559098

This helps to suppress the vmlinux.lds file.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/.gitignore | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 arch/openrisc/kernel/.gitignore

diff --git a/arch/openrisc/kernel/.gitignore b/arch/openrisc/kernel/.gitignore
new file mode 100644
index 0000000..c5f676c
--- /dev/null
+++ b/arch/openrisc/kernel/.gitignore
@@ -0,0 +1 @@
+vmlinux.lds
-- 
2.9.3

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#1559109 — [PATCH 13/22] openrisc: Fix the bitmask for the unit present register

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 13/22] openrisc: Fix the bitmask for the unit present register
Message-ID	<sZFM6-3B6-33@gated-at.bofh.it>
In reply to	#1559098

From: Sebastian Macke <sebastian@macke.de>

The bits were swapped, as per spec and processor implementation the
power management present bit is 9 and PIC bit is 8. This patch brings
the definitions into spec.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
[shorne@gmail.com: Added commit body]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/spr_defs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/openrisc/include/asm/spr_defs.h b/arch/openrisc/include/asm/spr_defs.h
index 5dbc668..367dac7 100644
--- a/arch/openrisc/include/asm/spr_defs.h
+++ b/arch/openrisc/include/asm/spr_defs.h
@@ -152,8 +152,8 @@
 #define SPR_UPR_MP	   0x00000020  /* MAC present */
 #define SPR_UPR_DUP	   0x00000040  /* Debug unit present */
 #define SPR_UPR_PCUP	   0x00000080  /* Performance counters unit present */
-#define SPR_UPR_PMP	   0x00000100  /* Power management present */
-#define SPR_UPR_PICP	   0x00000200  /* PIC present */
+#define SPR_UPR_PICP	   0x00000100  /* PIC present */
+#define SPR_UPR_PMP	   0x00000200  /* Power management present */
 #define SPR_UPR_TTP	   0x00000400  /* Tick timer present */
 #define SPR_UPR_RES	   0x00fe0000  /* Reserved */
 #define SPR_UPR_CUP	   0xff000000  /* Context units present */
-- 
2.9.3

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#1559110 — [PATCH 22/22] openrisc: head: Move init strings to rodata section

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 22/22] openrisc: head: Move init strings to rodata section
Message-ID	<sZFM7-3B6-39@gated-at.bofh.it>
In reply to	#1559098

The strings used during the head/init phase of openrisc bootup were
stored in the executable section of the binary.

This causes compilation to fail when using CONFIG_DEBUG_INFO with
error:
 Error: unaligned opcodes detected in executable segment

Also, this patch removes unused strings.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/head.S | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index a22f1fc..573e131 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -1530,11 +1530,7 @@ ENTRY(_early_uart_init)
 	l.jr	r9
 	l.nop
 
-_string_copying_linux:
-	.string "\n\n\n\n\n\rCopying Linux... \0"
-
-_string_ok_booting:
-	.string "Ok, booting the kernel.\n\r\0"
+	.section .rodata
 
 _string_unhandled_exception:
 	.string "\n\rRunarunaround: Unhandled exception 0x\0"
@@ -1545,12 +1541,6 @@ _string_epc_prefix:
 _string_nl:
 	.string "\n\r\0"
 
-	.global	_string_esr_irq_bug
-_string_esr_irq_bug:
-	.string "\n\rESR external interrupt bug, for details look into entry.S\n\r\0"
-
-
-
 /* ========================================[ page aligned structures ]=== */
 
 /*
-- 
2.9.3

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#1559111 — [PATCH 07/22] openrisc: add atomic bitops

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 07/22] openrisc: add atomic bitops
Message-ID	<sZFM6-3B6-35@gated-at.bofh.it>
In reply to	#1559098

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

This utilize the load-link/store-conditional l.lwa and l.swa
instructions to implement the atomic bitops.
When those instructions are not available emulation is provided.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by
Alan Cox https://lkml.org/lkml/2014/7/23/666]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/bitops.h        |   2 +-
 arch/openrisc/include/asm/bitops/atomic.h | 103 ++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/bitops/atomic.h

diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
index 3003cda..689f568 100644
--- a/arch/openrisc/include/asm/bitops.h
+++ b/arch/openrisc/include/asm/bitops.h
@@ -45,7 +45,7 @@
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 
-#include <asm-generic/bitops/atomic.h>
+#include <asm/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
diff --git a/arch/openrisc/include/asm/bitops/atomic.h b/arch/openrisc/include/asm/bitops/atomic.h
new file mode 100644
index 0000000..7d7f3a4
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops/atomic.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_BITOPS_ATOMIC_H
+#define __ASM_OPENRISC_BITOPS_ATOMIC_H
+
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%1)	\n"
+		"	l.or	%0,%0,%2	\n"
+		"	l.swa	0(%1),%0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(tmp)
+		: "r"(p), "r"(mask)
+		: "cc", "memory");
+}
+
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%1)	\n"
+		"	l.and	%0,%0,%2	\n"
+		"	l.swa	0(%1),%0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(tmp)
+		: "r"(p), "r"(~mask)
+		: "cc", "memory");
+}
+
+static inline void change_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%1)	\n"
+		"	l.xor	%0,%0,%2	\n"
+		"	l.swa	0(%1),%0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(tmp)
+		: "r"(p), "r"(mask)
+		: "cc", "memory");
+}
+
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old;
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%2)	\n"
+		"	l.or	%1,%0,%3	\n"
+		"	l.swa	0(%2),%1	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(old), "=&r"(tmp)
+		: "r"(p), "r"(mask)
+		: "cc", "memory");
+
+	return (old & mask) != 0;
+}
+
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old;
+	unsigned long tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%2)	\n"
+		"	l.and	%1,%0,%3	\n"
+		"	l.swa	0(%2),%1	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(old), "=&r"(tmp)
+		: "r"(p), "r"(~mask)
+		: "cc", "memory");
+
+	return (old & mask) != 0;
+}
+
+#endif /* __ASM_OPENRISC_BITOPS_ATOMIC_H */
-- 
2.9.3

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#1559167 — Re: [PATCH 07/22] openrisc: add atomic bitops

From	kbuild test robot <lkp@intel.com>
Date	2017-01-15 06:40 +0100
Subject	Re: [PATCH 07/22] openrisc: add atomic bitops
Message-ID	<sZLHQ-77S-7@gated-at.bofh.it>
In reply to	#1559111

[Multipart message — attachments visible in raw view] — view raw

Hi Stefan,

[auto build test ERROR on linus/master]
[also build test ERROR on v4.10-rc3 next-20170113]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Stafford-Horne/Openrisc-patchees-from-backlog-for-4-11/20170115-121623
config: openrisc-or1ksim_defconfig (attached as .config)
compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=openrisc 

All errors (new ones prefixed by >>):

   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   net/core/dev.c: In function 'validate_xmit_skb_list':
   net/core/dev.c:2989:39: warning: 'tail' may be used uninitialized in this function
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
--
   arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
>> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
   arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
   arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.

vim +70 arch/openrisc/include/asm/bitops/atomic.h

    64	{
    65		unsigned long mask = BIT_MASK(nr);
    66		unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
    67		unsigned long old;
    68		unsigned long tmp;
    69	
  > 70		__asm__ __volatile__(
    71			"1:	l.lwa	%0,0(%2)	\n"
  > 72			"	l.or	%1,%0,%3	\n"
    73			"	l.swa	0(%2),%1	\n"
    74			"	l.bnf	1b		\n"
    75			"	 l.nop			\n"

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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#1559179 — Re: [PATCH 07/22] openrisc: add atomic bitops

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 09:30 +0100
Subject	Re: [PATCH 07/22] openrisc: add atomic bitops
Message-ID	<sZOml-gT-9@gated-at.bofh.it>
In reply to	#1559167

Hello,

On Sun, Jan 15, 2017 at 01:42:56PM +0800, kbuild test robot wrote:
> Hi Stefan,
> 
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.10-rc3 next-20170113]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> 
> url:    https://github.com/0day-ci/linux/commits/Stafford-Horne/Openrisc-patchees-from-backlog-for-4-11/20170115-121623
> config: openrisc-or1ksim_defconfig (attached as .config)
> compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1
> reproduce:
>         wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=openrisc 
> 
> All errors (new ones prefixed by >>):
> 
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    net/core/dev.c: In function 'validate_xmit_skb_list':
>    net/core/dev.c:2989:39: warning: 'tail' may be used uninitialized in this function
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:35: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:37: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:90: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:92: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
> --
>    arch/openrisc/include/asm/bitops/atomic.h: Assembler messages:
> >> arch/openrisc/include/asm/bitops/atomic.h:70: Error: unknown opcode2 `l.lwa'.
> >> arch/openrisc/include/asm/bitops/atomic.h:72: Error: unknown opcode2 `l.swa'.
>    arch/openrisc/include/asm/bitops/atomic.h:18: Error: unknown opcode2 `l.lwa'.
>    arch/openrisc/include/asm/bitops/atomic.h:20: Error: unknown opcode2 `l.swa'.
> 
> vim +70 arch/openrisc/include/asm/bitops/atomic.h
> 
>     64	{
>     65		unsigned long mask = BIT_MASK(nr);
>     66		unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
>     67		unsigned long old;
>     68		unsigned long tmp;
>     69	
>   > 70		__asm__ __volatile__(
>     71			"1:	l.lwa	%0,0(%2)	\n"
>   > 72			"	l.or	%1,%0,%3	\n"
>     73			"	l.swa	0(%2),%1	\n"
>     74			"	l.bnf	1b		\n"
>     75			"	 l.nop			\n"
> 

All of these are due to the lwa/swa instructions.  A toolchain from the
last 2 years would be needed to build these instructions.  Can I suggest
that the test chain be updated?  I would suggest musl. But there are
currently two options openrisc team is maintaining.

:: or1k-musl-linux- chain ::

Get it here:
https://github.com/openrisc/or1k-gcc/tree/musl-5.4.0/gcc
  - build using
    https://github.com/openrisc/musl-cross
    (would suggest my pull request - will merge soon
     https://github.com/openrisc/musl-cross/pull/1)


:: or1k-elf- chain ::

Get it here:
  https://github.com/openrisc/or1k-gcc/tree/or1k-5.4.0/gcc
  - build using baremetal/newlib
    https://github.com/openrisc/newlib
  - instructions
    http://openrisc.io/newlib/building.html

- Stafford

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#1559112 — [PATCH 09/22] openrisc: add optimized atomic operations

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 09/22] openrisc: add optimized atomic operations
Message-ID	<sZFM7-3B6-37@gated-at.bofh.it>
In reply to	#1559098

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Using the l.lwa and l.swa atomic instruction pair.
Most openrisc processor cores provide these instructions now. If the
instructions are not available emulation is provided.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by
Alan Cox https://lkml.org/lkml/2014/7/23/666]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/Kbuild   |  1 -
 arch/openrisc/include/asm/atomic.h | 53 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/atomic.h

diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 15e6ed5..1cedd63 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,7 +1,6 @@
 
 header-y += ucontext.h
 
-generic-y += atomic.h
 generic-y += auxvec.h
 generic-y += barrier.h
 generic-y += bitsperlong.h
diff --git a/arch/openrisc/include/asm/atomic.h b/arch/openrisc/include/asm/atomic.h
new file mode 100644
index 0000000..67f0b30
--- /dev/null
+++ b/arch/openrisc/include/asm/atomic.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_ATOMIC_H
+#define __ASM_OPENRISC_ATOMIC_H
+
+#include <linux/types.h>
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+	int tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%1)	\n"
+		"	l.add	%0,%0,%2	\n"
+		"	l.swa	0(%1),%0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(tmp)
+		: "r"(&v->counter), "r"(i)
+		: "cc", "memory");
+
+	return tmp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+	int tmp;
+
+	__asm__ __volatile__(
+		"1:	l.lwa	%0,0(%1)	\n"
+		"	l.sub	%0,%0,%2	\n"
+		"	l.swa	0(%1),%0	\n"
+		"	l.bnf	1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(tmp)
+		: "r"(&v->counter), "r"(i)
+		: "cc", "memory");
+
+	return tmp;
+}
+
+#define atomic_add_return	atomic_add_return
+#define atomic_sub_return	atomic_sub_return
+
+#include <asm-generic/atomic.h>
+
+#endif /* __ASM_OPENRISC_ATOMIC_H */
-- 
2.9.3

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#1559113 — [PATCH 18/22] MAINTAINERS: Add the openrisc official repository

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 18/22] MAINTAINERS: Add the openrisc official repository
Message-ID	<sZFM7-3B6-41@gated-at.bofh.it>
In reply to	#1559098

The openrisc official repository and patch work happens currently on
github. Add the repo for reference.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5f0420a..d55d0d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9171,6 +9171,7 @@ OPENRISC ARCHITECTURE
 M:	Jonas Bonn <jonas@southpole.se>
 M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 M:	Stafford Horne <shorne@gmail.com>
+T:	git git://github.com/openrisc/linux.git
 L:	openrisc@lists.librecores.org
 W:	http://openrisc.io
 S:	Maintained
-- 
2.9.3

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#1559114 — [PATCH 20/22] openrisc: entry: Whitespace and comment cleanups

From	Stafford Horne <shorne@gmail.com>
Date	2017-01-15 00:20 +0100
Subject	[PATCH 20/22] openrisc: entry: Whitespace and comment cleanups
Message-ID	<sZFM7-3B6-43@gated-at.bofh.it>
In reply to	#1559098

Cleanups to whitespace and add some comments. Reading through the delay
slot logic I noticed some things:
 - Delay slot instructions were not indented
 - Some comments are not lined up
 - Use tabs and spaces consistent with other code

No functional change

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/kernel/entry.S | 38 ++++++++++++++++++--------------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index ba1a361..daae2a4 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -228,7 +228,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
 	 * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
 	 */
 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
-	l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+	l.lwz   r6,PT_PC(r3)               // address of an offending insn
 	l.lwz   r6,0(r6)                   // instruction that caused pf
 
 	l.srli  r6,r6,26                   // check opcode for jump insn
@@ -244,49 +244,47 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
 	l.bf    8f
 	l.sfeqi r6,0x12                    // l.jalr
 	l.bf    8f
-
-	l.nop
+	 l.nop
 
 	l.j     9f
-	l.nop
-8:
+	 l.nop
 
-	l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+8: // offending insn is in delay slot
+	l.lwz   r6,PT_PC(r3)               // address of an offending insn
 	l.addi  r6,r6,4
 	l.lwz   r6,0(r6)                   // instruction that caused pf
 	l.srli  r6,r6,26                   // get opcode
-9:
+9: // offending instruction opcode loaded in r6
 
 #else
 
-	l.mfspr r6,r0,SPR_SR		   // SR
-//	l.lwz	r6,PT_SR(r3)		   // ESR
-	l.andi	r6,r6,SPR_SR_DSX	   // check for delay slot exception
-	l.sfeqi	r6,0x1			   // exception happened in delay slot
-	l.bnf	7f
-	l.lwz	r6,PT_PC(r3)		   // address of an offending insn
+	l.mfspr r6,r0,SPR_SR               // SR
+	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
+	l.sfeqi r6,0x1                     // exception happened in delay slot
+	l.bnf   7f
+	 l.lwz  r6,PT_PC(r3)               // address of an offending insn
 
-	l.addi	r6,r6,4			   // offending insn is in delay slot
+	l.addi	r6,r6,4                    // offending insn is in delay slot
 7:
 	l.lwz   r6,0(r6)                   // instruction that caused pf
 	l.srli  r6,r6,26                   // check opcode for write access
 #endif
 
-	l.sfgeui r6,0x33		   // check opcode for write access
+	l.sfgeui r6,0x33                   // check opcode for write access
 	l.bnf   1f
 	l.sfleui r6,0x37
 	l.bnf   1f
 	l.ori   r6,r0,0x1                  // write access
 	l.j     2f
-	l.nop
+	 l.nop
 1:	l.ori   r6,r0,0x0                  // !write access
 2:
 
 	/* call fault.c handler in or32/mm/fault.c */
 	l.jal   do_page_fault
-	l.nop
+	 l.nop
 	l.j     _ret_from_exception
-	l.nop
+	 l.nop
 
 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
@@ -306,9 +304,9 @@ EXCEPTION_ENTRY(_insn_page_fault_handler)
 
 	/* call fault.c handler in or32/mm/fault.c */
 	l.jal   do_page_fault
-	l.nop
+	 l.nop
 	l.j     _ret_from_exception
-	l.nop
+	 l.nop
 
 
 /* ---[ 0x500: Timer exception ]----------------------------------------- */
-- 
2.9.3

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#1559163

From	Guenter Roeck <linux@roeck-us.net>
Date	2017-01-15 06:20 +0100
Message-ID	<sZLot-6XD-3@gated-at.bofh.it>
In reply to	#1559098

On 01/14/2017 03:07 PM, Stafford Horne wrote:
> Hi All,
>
> This is another set of patches which I have been pulling out of the
> openrisc backlogs. Its a bit of a process since I need to cleanup commit
> messages, review and test the patches.
>
> The interesting things here are:
>  - optimized memset and memcpy routines, ~20% boot time saving
>  - support for cpu idling
>  - adding support for l.swa and l.lwa atomic operations (in spec from 2014)
>  - use atomics to implement: bitops, cmpxchg, futex, spinlocks
>  - the atomics are in preparation for SMP support
>
> Testing:
> I have used the kselftests to validate the changes especially the futex
> operations with the futex test. Other atomic operations are common so no
> explicit testing.
>
> Note for testers:
> The l.swa and l.lwa emulation is broken in qemu openrisc port. I have sent
> patches [1] to qemu-devel to fix the qemu issues.
>

Thanks a lot for the note. Cherry-picked and applied ...

Are you going to add the series to -next ? That would give it some automatic
test exposure (including the various auto-builders).

Anyway, today's -next gets a warning traceback as attached. That happens even
with the above mentioned patch applied to qemu.

Guenter

---

OpenRISC Linux -- http://openrisc.io
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ./include/linux/jump_label.h:198 0xc02d758c
static_key_slow_inc used before call to jump_label_init
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 4.10.0-rc3-next-20170113 #1
Stack dump [0xc0385f3c]:
sp + 00: 0xc0385f3c
sp + 04: 0xc0385f60
sp + 08: 0xc047a0b4
sp + 12: 0xc0303662
sp + 16: 0x00000000
sp + 20: 0xc02d758c
sp + 24: 0x00000009
sp + 28: 0x000000c6
sp + 32: 0xc0167bc0
sp + 36: 0xc0385f68
sp + 40: 0xc000b5d8
sp + 44: 0x00000000
sp + 48: 0x00000000
sp + 52: 0xc0303662
sp + 56: 0x000000c6
sp + 60: 0xc02d758c
sp + 64: 0xc0385f9c
sp + 68: 0xc0385fb0
sp + 72: 0xc0483954
sp + 76: 0xc04839b0
sp + 80: 0xc1fff1e0
sp + 84: 0xc047a00c
sp + 88: 0x00000000
sp + 92: 0xc000b620
sp + 96: 0xc030367f
sp + 100: 0xc0385fb0
sp + 104: 0xc0385fb0
sp + 108: 0xc0483930
sp + 112: 0xc02d758c
sp + 116: 0xc02e1cc4
sp + 120: 0x00000000
sp + 124: 0x00000000
sp + 128: 0xc03a6798
sp + 132: 0xc0385fd8
sp + 136: 0xc047a014
sp + 140: 0xc047a02c
sp + 144: 0xc03beb14
sp + 148: 0xc1fff1e0
sp + 152: 0xc03a68e0
sp + 156: 0xc02e0070
sp + 160: 0xc03b9e74
sp + 164: 0xc03beb14
sp + 168: 0xc0386000
sp + 172: 0x00000000
sp + 176: 0x00000000
sp + 180: 0x00000000
sp + 184: 0x00000000
sp + 188: 0x00000000
sp + 192: 0x00000000

  [<c02d758c>]

  [<c0167bc0>]

  [<c000b5d8>]

  [<c02d758c>]

  [<c000b620>]

  [<c02d758c>]

  [<c03a6798>]

  [<c03a68e0>]

  [<c03b9e74>]

  =======================
---[ end trace 0000000000000000 ]---

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Page 1 of 2 [1] 2 Next page →

csiph-web

[PATCH 00/22] Openrisc patchees from backlog for 4.11

Contents

#1559098 — [PATCH 00/22] Openrisc patchees from backlog for 4.11

#1559099 — [PATCH 19/22] scripts/checkstack.pl: Add openrisc support

#1559100 — [PATCH 16/22] openrisc: Add optimized memcpy routine

#1559101 — [PATCH 12/22] openrisc: remove unnecessary stddef.h include

#1559102 — [PATCH 21/22] openrisc: entry: Fix delay slot detection

#1559103 — [PATCH 14/22] openrisc: Initial support for the idle state

#1559104 — [PATCH 15/22] openrisc: Add optimized memset

#1559105 — [PATCH 10/22] openrisc: add spinlock implementation

#1559106 — [PATCH 11/22] openrisc: add futex_atomic_* implementations

#1559107 — [PATCH 03/22] openrisc: tlb miss handler optimizations

#1559108 — [PATCH 17/22] openrisc: Add .gitignore

#1559109 — [PATCH 13/22] openrisc: Fix the bitmask for the unit present register

#1559110 — [PATCH 22/22] openrisc: head: Move init strings to rodata section

#1559111 — [PATCH 07/22] openrisc: add atomic bitops

#1559167 — Re: [PATCH 07/22] openrisc: add atomic bitops

#1559179 — Re: [PATCH 07/22] openrisc: add atomic bitops

#1559112 — [PATCH 09/22] openrisc: add optimized atomic operations

#1559113 — [PATCH 18/22] MAINTAINERS: Add the openrisc official repository

#1559114 — [PATCH 20/22] openrisc: entry: Whitespace and comment cleanups

#1559163