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[PATCH v10 0/5] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing

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  [PATCH v10 0/5] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
    [PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
      Re: [PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing kbuild test robot <lkp@intel.com> - 2016-12-16 22:20 +0100
    [PATCH v10 2/5] x86/elf: add HWCAP2 to expose ring 3 MONITOR/MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
    [PATCH v10 3/5] x86/cpufeature: add RING3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
    [PATCH v10 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100

#1543635 — [PATCH v10 0/5] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing

Following patches enable the use of the feature that allows
the some Intel Xeon Phi processors to use MONITOR/MWAIT instructions
outside ring 0. This feature allows userspace application to use
more efficient synchronization operations, which improves performance
and energy efficiency. 

v10:
Included Piotr's patch for Knights Mill
Included Dave's comments from internal review
Rewritten commit messages
Removed x86_64 config requirement
Fixed kernel boot parameter description
Used set_bit to update HWCAP2 bit
Rebased to kernel 4.9

v9:
Removed PHI prefix from defines

v8:
Updated commit messages
Removed logging
Used msr_set/clear_bit functions instesd of wrmsrl
Fixed documentation
Renamed HWCAP2_PHIR3MWAIT to HWCAP2_RING3MWAIT

v7:
Changed order of the patches
Changed the name of MSR to MSR_MISC_FEATURE_ENABLES
Used bit 25 from word 3 to expose feature

v6: 

v5:
Added phir3mwait=disable cmdline switch
Fixed typos

v4:
Wrapped the enabling code by CONFIG_X86_64
Moved probe_ function call from early_intel_init to intel_init
Fixed commit messages

v3:
Included Dave's and Thomas' comments

v2:
Added check MSR before wrmsrl
Shortened names
Used Word 3 for feature init_scattered_cpuid_features()
Fixed commit messages

Grzegorz Andrejczuk (4):
  x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit
  x86/elf: add HWCAP2 to expose ring 3 MONITOR/MWAIT
  x86/cpufeature: add RING3MWAIT to CPU features
  x86/cpufeature: enable RING3MWAIT for Knights Landing

Piotr Luc (1):
  x86/cpufeature: enable RING3MWAIT for Knights Mill

 Documentation/kernel-parameters.txt |  3 +++
 arch/x86/include/asm/cpufeatures.h  |  2 +-
 arch/x86/include/asm/elf.h          |  9 +++++++++
 arch/x86/include/asm/msr-index.h    |  6 ++++++
 arch/x86/include/uapi/asm/hwcap2.h  |  7 +++++++
 arch/x86/kernel/cpu/common.c        |  3 +++
 arch/x86/kernel/cpu/intel.c         | 36 ++++++++++++++++++++++++++++++++++++
 7 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/include/uapi/asm/hwcap2.h

-- 
2.5.1

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#1543636 — [PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing

This patch enables ring 3 MONITOR/MWAIT for Intel Xeon Phi x200
codenamed Knights Landing.

The patch:
- Sets CPU feature X86_FEATURE_RING3MWAIT.
- Sets HWCAP2_RING3MWAIT bit in ELF_HWCAP2.
- Adds the ring3mwait=disable command line parameter.
- Sets bit 1 of the MSR MISC_FEATURE_ENABLES or clears it when
  the ring3mwait=disable command line parameter is used.

Presence of this feature cannot be detected automatically
(by reading any other MSR) therefore it is required to
explicitly check for the family and model of the CPU before attempting
to enable it.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 Documentation/kernel-parameters.txt |  3 +++
 arch/x86/kernel/cpu/intel.c         | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 37babf9..c8bca65 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3734,6 +3734,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 	rhash_entries=	[KNL,NET]
 			Set number of hash buckets for route cache
 
+	ring3mwait=	[KNL]
+		disable	Disable ring 3 MONITOR/MWAIT feature on supported CPUs.
+
 	ro		[KNL] Mount root device read-only on boot
 
 	rodata=		[KNL]
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..70d4985 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -14,6 +14,8 @@
 #include <asm/bugs.h>
 #include <asm/cpu.h>
 #include <asm/intel-family.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
 
 #ifdef CONFIG_X86_64
 #include <linux/topology.h>
@@ -61,6 +63,36 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
 	}
 }
 
+static int ring3mwait_disabled __read_mostly;
+
+static int __init ring3mwait_disable(char *__unused)
+{
+	ring3mwait_disabled = 1;
+	return 1;
+}
+__setup("ring3mwait=disable", ring3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Ring 3 MONITOR/MWAIT feature cannot be detected without
+	 * cpu model and family comparison.
+	 */
+	if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+		return;
+
+	if (ring3mwait_disabled) {
+		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
+			      MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+		return;
+	}
+
+	msr_set_bit(MSR_MISC_FEATURE_ENABLES,
+		    MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
+	set_bit(HWCAP2_RING3MWAIT, &ELF_HWCAP2);
+}
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;
@@ -565,6 +597,8 @@ static void init_intel(struct cpuinfo_x86 *c)
 		detect_vmx_virtcap(c);
 
 	init_intel_energy_perf(c);
+
+	probe_xeon_phi_r3mwait(c);
 }
 
 #ifdef CONFIG_X86_32
-- 
2.5.1

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#1543757 — Re: [PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing

[Multipart message — attachments visible in raw view] — view raw

Hi Grzegorz,

[auto build test WARNING on tip/x86/core]
[also build test WARNING on v4.9 next-20161216]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Grzegorz-Andrejczuk/Enabling-Ring-3-MONITOR-MWAIT-feature-for-Knights-Landing/20161217-041756
config: i386-randconfig-i1-201650 (attached as .config)
compiler: gcc-4.8 (Debian 4.8.4-1) 4.8.4
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All warnings (new ones prefixed by >>):

   arch/x86/kernel/cpu/intel.c: In function 'probe_xeon_phi_r3mwait':
>> arch/x86/kernel/cpu/intel.c:93:2: warning: passing argument 2 of 'set_bit' from incompatible pointer type [enabled by default]
     set_bit(HWCAP2_RING3MWAIT, &ELF_HWCAP2);
     ^
   In file included from include/linux/bitops.h:36:0,
                    from include/linux/kernel.h:10,
                    from arch/x86/kernel/cpu/intel.c:1:
   arch/x86/include/asm/bitops.h:72:1: note: expected 'volatile long unsigned int *' but argument is of type 'unsigned int *'
    set_bit(long nr, volatile unsigned long *addr)
    ^

vim +/set_bit +93 arch/x86/kernel/cpu/intel.c

    77		/*
    78		 * Ring 3 MONITOR/MWAIT feature cannot be detected without
    79		 * cpu model and family comparison.
    80		 */
    81		if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
    82			return;
    83	
    84		if (ring3mwait_disabled) {
    85			msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
    86				      MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
    87			return;
    88		}
    89	
    90		msr_set_bit(MSR_MISC_FEATURE_ENABLES,
    91			    MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
    92		set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
  > 93		set_bit(HWCAP2_RING3MWAIT, &ELF_HWCAP2);
    94	}
    95	
    96	static void early_init_intel(struct cpuinfo_x86 *c)
    97	{
    98		u64 misc_enable;
    99	
   100		/* Unmask CPUID levels if masked: */
   101		if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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#1543637 — [PATCH v10 2/5] x86/elf: add HWCAP2 to expose ring 3 MONITOR/MWAIT

This patch introduces ELF_HWCAP2 variable for x86 and reserves one bit
in it to expose the ring 3 MONITOR/MWAIT.

HWCAP variables contain bitmask which can be used by userspace
applications to detect what instruction sets are supported by CPU.
On x86 architecture information about CPU capabilities can be checked
via CPUID instructions, unfortunately presence of ring 3 MONITOR/MWAIT
feature cannot be checked this way. ELF_HWCAP cannot be used as well,
because on x86 it is set to CPUID[1].EDX which means that all bits
are reserved there.

HWCAP2 approach was chosen because it reuses existing solution present
in other architectures, so only minor modifications are required to the
kernel and userspace applications. When ELF_HWCAP2 is defined
kernel maps it to AT_HWCAP2 during the start of the application.
This way the ring 3 MONITOR/MWAIT feature can be detected using getauxval()
API in a simple and fast manner.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 arch/x86/include/asm/elf.h         | 9 +++++++++
 arch/x86/include/uapi/asm/hwcap2.h | 7 +++++++
 arch/x86/kernel/cpu/common.c       | 3 +++
 3 files changed, 19 insertions(+)
 create mode 100644 arch/x86/include/uapi/asm/hwcap2.h

diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index e7f155c..59703aa 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -258,6 +258,15 @@ extern int force_personality32;
 
 #define ELF_HWCAP		(boot_cpu_data.x86_capability[CPUID_1_EDX])
 
+extern unsigned int elf_hwcap2;
+
+/*
+ * HWCAP2 supplies mask with kernel enabled CPU features, so that
+ * the application can discover that it can safely use them.
+ * The bits are defined in uapi/asm/hwcap2.h.
+ */
+#define ELF_HWCAP2		elf_hwcap2
+
 /* This yields a string that ld.so will use to load implementation
    specific libraries for optimization.  This is more specific in
    intent than poking at uname or /proc/cpuinfo.
diff --git a/arch/x86/include/uapi/asm/hwcap2.h b/arch/x86/include/uapi/asm/hwcap2.h
new file mode 100644
index 0000000..0bd2be5
--- /dev/null
+++ b/arch/x86/include/uapi/asm/hwcap2.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_X86_HWCAP2_H
+#define _ASM_X86_HWCAP2_H
+
+/* MONITOR/MWAIT enabled in Ring 3 */
+#define HWCAP2_RING3MWAIT		(1 << 0)
+
+#endif
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cc9e980..217697b 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -35,6 +35,7 @@
 #include <asm/desc.h>
 #include <asm/fpu/internal.h>
 #include <asm/mtrr.h>
+#include <asm/hwcap2.h>
 #include <linux/numa.h>
 #include <asm/asm.h>
 #include <asm/bugs.h>
@@ -51,6 +52,8 @@
 
 #include "cpu.h"
 
+unsigned int elf_hwcap2 __read_mostly;
+
 /* all of these masks are initialized in setup_cpu_local_masks() */
 cpumask_var_t cpu_initialized_mask;
 cpumask_var_t cpu_callout_mask;
-- 
2.5.1

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#1543638 — [PATCH v10 3/5] x86/cpufeature: add RING3MWAIT to CPU features

This commit adds software-defined CPUID bit for the non-architectural ring 3
MONITOR/MWAIT feature.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index a396292..dc0255e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
 #define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_RING3MWAIT	( 3*32+25) /* ring 3 MONITOR/MWAIT */
 #define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */
 #define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */
 #define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
-- 
2.5.1

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#1543639 — [PATCH v10 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

This patch defines new MSR MISC_FEATURE_ENABLES (0x140).
On supported CPUs if bit 1 of this new register is set,
then calling MONITOR and MWAIT instructions outside of ring 0 will
not cause invalid-opcode exception.

The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is
the relevant documentation:

Hex   Dec  Name                     Scope
140H  320  MISC_FEATURE_ENABLES     Thread
           0    Reserved
           1    If set to 1, the MONITOR and MWAIT instructions do not
                cause invalid-opcode exceptions when executed with CPL > 0
                or in virtual-8086 mode. If MWAIT is executed when CPL > 0
                or in virtual-8086 mode, and if EAX indicates a C-state
                other than C0 or C1, the instruction operates as if EAX
                indicated the C-state C1.
           63:2 Reserved

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 arch/x86/include/asm/msr-index.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 78f3760..55ffae0 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -539,6 +539,12 @@
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
+/* MISC_FEATURE_ENABLES non-architectural features */
+#define MSR_MISC_FEATURE_ENABLES		0x00000140
+
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT		1
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT		(1ULL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
+
 #define MSR_IA32_TSC_DEADLINE		0x000006E0
 
 /* P4/Xeon+ specific */
-- 
2.5.1

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