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Groups > linux.kernel > #1543638
| From | Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v10 3/5] x86/cpufeature: add RING3MWAIT to CPU features |
| Date | 2016-12-16 19:10 +0100 |
| Message-ID | <sP57c-75S-27@gated-at.bofh.it> (permalink) |
| References | <sP57b-75S-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
This commit adds software-defined CPUID bit for the non-architectural ring 3 MONITOR/MWAIT feature. Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> --- arch/x86/include/asm/cpufeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index a396292..dc0255e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -100,7 +100,7 @@ #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ -/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ +#define X86_FEATURE_RING3MWAIT ( 3*32+25) /* ring 3 MONITOR/MWAIT */ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ -- 2.5.1
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[PATCH v10 0/5] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
[PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
Re: [PATCH v10 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing kbuild test robot <lkp@intel.com> - 2016-12-16 22:20 +0100
[PATCH v10 2/5] x86/elf: add HWCAP2 to expose ring 3 MONITOR/MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
[PATCH v10 3/5] x86/cpufeature: add RING3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
[PATCH v10 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-16 19:10 +0100
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