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Groups > linux.kernel > #1452961 > unrolled thread

[PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom

Started byXing Zheng <zhengxing@rock-chips.com>
First post2016-08-01 05:50 +0200
Last post2016-08-01 06:00 +0200
Articles 6 — 1 participant

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Contents

  [PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200
    [PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200
    [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200
    [PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200
    [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200
    [PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:00 +0200

#1452961 — [PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-08-01 05:50 +0200
Subject[PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom
Message-ID<s1coN-Tv-3@gated-at.bofh.it>
Hi:
  In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.


Elaine Zhang (1):
  clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

Xing Zheng (5):
  clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
  clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
  clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
  clk: rockchip: rk3399: Add support frac mode frequencies

 drivers/clk/rockchip/clk-rk3399.c      |   35 +++++++++++++++++++++++++-------
 include/dt-bindings/clock/rk3399-cru.h |    2 ++
 2 files changed, 30 insertions(+), 7 deletions(-)

-- 
1.7.9.5

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#1452962 — [PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-08-01 05:50 +0200
Subject[PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
Message-ID<s1coO-Tv-11@gated-at.bofh.it>
In reply to#1452961
Export these source clocks for usbphy.


Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 	GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-	GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+	GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(13), 12, GFLAGS),
-	GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+	GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(13), 12, GFLAGS),
 	MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
-- 
1.7.9.5

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#1452963 — [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-08-01 05:50 +0200
Subject[PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
Message-ID<s1coO-Tv-9@gated-at.bofh.it>
In reply to#1452961
We export some clock IDs for the usb phy 480m source clocks.


Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 include/dt-bindings/clock/rk3399-cru.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -131,6 +131,8 @@
 #define SCLK_DPHY_RX0_CFG		165
 #define SCLK_RMII_SRC			166
 #define SCLK_PCIEPHY_REF100M		167
+#define SCLK_USBPHY0_480M_SRC		168
+#define SCLK_USBPHY1_480M_SRC		169
 
 #define DCLK_VOP0			180
 #define DCLK_VOP1			181
-- 
1.7.9.5

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#1452967 — [PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-08-01 05:50 +0200
Subject[PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
Message-ID<s1coO-Tv-19@gated-at.bofh.it>
In reply to#1452961
We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
 	RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
 	RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
 	RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
+	RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
 	RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
 	RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
+	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
 	RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
 	RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
 	{ /* sentinel */ },
-- 
1.7.9.5

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#1452970 — [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-08-01 05:50 +0200
Subject[PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Message-ID<s1coO-Tv-21@gated-at.bofh.it>
In reply to#1452961
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..ad3860a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
 	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-			RK3399_CLKGATE_CON(6), 12, GFLAGS),
-	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 13, GFLAGS),
+	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+			RK3399_CLKGATE_CON(6), 12, GFLAGS),
 	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

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#1452971 — [PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-08-01 06:00 +0200
Subject[PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Message-ID<s1cyt-WE-7@gated-at.bofh.it>
In reply to#1452961
From: Elaine Zhang <zhangqing@rock-chips.com>

allow aclk_pcie and aclk_perf_pcie disabled when unused.


Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 74afec0..4a15ce5b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
 			RK3399_CLKGATE_CON(5), 4, GFLAGS),
 
-	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
 			RK3399_CLKGATE_CON(20), 2, GFLAGS),
-	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
 			RK3399_CLKGATE_CON(20), 10, GFLAGS),
 	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(20), 12, GFLAGS),
-- 
1.7.9.5

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