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Groups > linux.kernel > #1452963
| From | Xing Zheng <zhengxing@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs |
| Date | 2016-08-01 05:50 +0200 |
| Message-ID | <s1coO-Tv-9@gated-at.bofh.it> (permalink) |
| References | <s1coN-Tv-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- include/dt-bindings/clock/rk3399-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5
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[PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200 [PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200 [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200 [PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200 [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 05:50 +0200 [PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 06:00 +0200
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