Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1283374 > unrolled thread
| Started by | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| First post | 2015-12-03 22:10 +0100 |
| Last post | 2015-12-08 21:30 +0100 |
| Articles | 20 — 3 participants |
Back to article view | Back to linux.kernel
[PATCH V6 00/26] Coresight integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:10 +0100
[PATCH V6 26/26] perf tools: adding coresight etm PMU record capabilities Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:10 +0100
[PATCH V6 08/26] coresight: etm3x: adding operation mode for etm_enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 11/26] coresight: etm3x: changing default trace configuration Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 18/26] coresight: etb10: implementing AUX space API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
Re: [PATCH V6 18/26] coresight: etb10: implementing AUX space API Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2015-12-11 15:10 +0100
Re: [PATCH V6 18/26] coresight: etb10: implementing AUX space API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-11 22:20 +0100
[PATCH V6 03/26] coresight: etm3x: unlocking tracers in default arch init Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 07/26] coresight: moving PM runtime operations to core framework Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 05/26] coresight: etm3x: implementing 'cpu_id()' API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 09/26] coresight: add API to get sink from path Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 01/26] coresight: etm3x: moving etm_readl/writel to header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 14/26] coresight: etm3x: adding perf_get/set_config() API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 17/26] coresight: adding operation mode for sink->enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 06/26] coresight: associating path with session rather than tracer Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
[PATCH V6 13/26] coresight: etm3x: implementing user/kernel mode tracing Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-03 22:20 +0100
Re: [PATCH V6 00/26] Coresight integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-08 21:30 +0100
Re: [PATCH V6 00/26] Coresight integration with perf Arnaldo Carvalho de Melo <acme@kernel.org> - 2015-12-08 21:40 +0100
Re: [PATCH V6 00/26] Coresight integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-10 22:30 +0100
Re: [PATCH V6 00/26] Coresight integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-12-08 21:30 +0100
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:10 +0100 |
| Subject | [PATCH V6 00/26] Coresight integration with perf |
| Message-ID | <qBJix-1Vy-3@gated-at.bofh.it> |
This patchset aims to integrate configuration and control of
the Coresight tracers with the perf sub-system.
The goal is to use PMUs to represent tracers and the auxiliary
buffer enhancement to collect processor traces. As such a lot
of work is done to move the current Coresight sysFS oriented
configuration and control commands to perf's AUX API.
For the time being the work concentrates on ETMv3 and ETB1.0
sink buffer. Work on ETMv4 and other type of sink buffers
will follow once a foundation has been established.
Best regards,
Mathieu
Changes since V5:
* Addressed Arnaldo's comment about using a struct perf_evlist rather
than a struct perf_session.
* Addressed kbuild test robot's anomaly report [1].
* Moved perf_aux_output_{begin|end} to etm_event_{start|stop} in
accordance with [2].
[1]. https://lkml.org/lkml/2015/11/30/46
[2]. http://thread.gmane.org/gmane.linux.kernel/2099328/focus=2099343
Changes since V4:
* Reworked the way event configuration information is kept, fixing
a few corner cases when doing per CPU tracing.
* Rebased on 4.4-rc1.
* Added 'Cc' to specific perf related patches in the hope of suscitating
interest from reviewers, i.e perf maintainers.
Changes since V3:
* Rebased to GKH's char-misc-next tree (e2d8680741ed).
Changes since V2:
* Rebased to v4.3.
* Used the -M option to "git format-patch".
* Decoupled tracers and path - both are now completely independent.
* Moved path enablement/release to Perf's add/del functions.
* Moved PM runtime operations to the coresight core rather than
individual drivers.
* Enhanced mutual exclusion scheme between perf and sysFS.
* Removed architecture specific define in perf cmd line tool.
* Got rid of unused fields in structure 'cs_buffers'.
* Enhanced changelog for patch 16/26.
Changes since V1:
* Fixed typos in typographical error in documentation.
* Moved to a multi session support scheme.
* Split static and dynamic tracer configuration.
* Fixed configuration for user and kernel space tracing.
* Using WARN_ON_ONCE() rather than WARN_ON().
* Implemented strategy to prevent tracers from being used simultaneously.
* Changed sink_ops::unset_buffer() to sink_ops::reset_buffer().
* Moves ETM's sysFS interface from driver core to dedicated file.
* Removed spinlock in "etm_cpu_id()".
* Aggregated PMU driver pieces in a single patch.
* Added user space changes and rebased everything to v4.3-rc5.
Mathieu Poirier (26):
coresight: etm3x: moving etm_readl/writel to header file
coresight: etm3x: moving sysFS entries to dedicated file
coresight: etm3x: unlocking tracers in default arch init
coresight: etm3x: splitting struct etm_drvdata
coresight: etm3x: implementing 'cpu_id()' API
coresight: associating path with session rather than tracer
coresight: moving PM runtime operations to core framework
coresight: etm3x: adding operation mode for etm_enable()
coresight: add API to get sink from path
coresight: etm3x: set progbit to stop trace collection
coresight: etm3x: changing default trace configuration
coresight: etm3x: consolidating initial config
coresight: etm3x: implementing user/kernel mode tracing
coresight: etm3x: adding perf_get/set_config() API
coresight: etm3x: implementing perf_enable/disable() API
coresight: etb10: moving to local atomic operations
coresight: adding operation mode for sink->enable()
coresight: etb10: implementing AUX space API
coresight: updating documentation to reflect integration with perf
perf: changing pmu::setup_aux() parameter to include event
coresight: etm-perf: new PMU driver for ETM tracers
coresight: introducing a global trace ID function
perf tools: making function set_max_cpu_num() non static
perf tools: adding perf_evlist to *info_priv_size()
perf tools: making coresight PMU listable
perf tools: adding coresight etm PMU record capabilities
Documentation/trace/coresight.txt | 138 +-
MAINTAINERS | 4 +
arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +-
arch/x86/kernel/cpu/perf_event_intel_pt.c | 5 +-
drivers/hwtracing/coresight/Kconfig | 1 +
drivers/hwtracing/coresight/Makefile | 4 +-
drivers/hwtracing/coresight/coresight-etb10.c | 277 +++-
drivers/hwtracing/coresight/coresight-etm-perf.c | 447 +++++
drivers/hwtracing/coresight/coresight-etm-perf.h | 32 +
drivers/hwtracing/coresight/coresight-etm.h | 143 +-
.../hwtracing/coresight/coresight-etm3x-sysfs.c | 1442 ++++++++++++++++
drivers/hwtracing/coresight/coresight-etm3x.c | 1754 +++++---------------
drivers/hwtracing/coresight/coresight-etm4x.c | 8 +-
drivers/hwtracing/coresight/coresight-funnel.c | 2 -
drivers/hwtracing/coresight/coresight-priv.h | 15 +
.../coresight/coresight-replicator-qcom.c | 4 -
drivers/hwtracing/coresight/coresight-replicator.c | 2 -
drivers/hwtracing/coresight/coresight-tmc.c | 7 +-
drivers/hwtracing/coresight/coresight-tpiu.c | 4 +-
drivers/hwtracing/coresight/coresight.c | 330 ++--
include/linux/coresight-pmu.h | 39 +
include/linux/coresight.h | 40 +-
include/linux/perf_event.h | 2 +-
kernel/events/ring_buffer.c | 2 +-
tools/perf/arch/arm/util/Build | 2 +
tools/perf/arch/arm/util/auxtrace.c | 48 +
tools/perf/arch/arm/util/cs_etm.c | 466 ++++++
tools/perf/arch/arm/util/cs_etm.h | 44 +
tools/perf/arch/arm/util/pmu.c | 34 +
tools/perf/arch/x86/util/intel-bts.c | 4 +-
tools/perf/arch/x86/util/intel-pt.c | 4 +-
tools/perf/config/Makefile | 17 +-
tools/perf/util/auxtrace.c | 8 +-
tools/perf/util/auxtrace.h | 7 +-
tools/perf/util/cpumap.c | 2 +-
tools/perf/util/cpumap.h | 1 +
36 files changed, 3753 insertions(+), 1590 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-etm-perf.c
create mode 100644 drivers/hwtracing/coresight/coresight-etm-perf.h
create mode 100644 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
create mode 100644 include/linux/coresight-pmu.h
create mode 100644 tools/perf/arch/arm/util/auxtrace.c
create mode 100644 tools/perf/arch/arm/util/cs_etm.c
create mode 100644 tools/perf/arch/arm/util/cs_etm.h
create mode 100644 tools/perf/arch/arm/util/pmu.c
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:10 +0100 |
| Subject | [PATCH V6 26/26] perf tools: adding coresight etm PMU record capabilities |
| Message-ID | <qBJiz-1Vy-35@gated-at.bofh.it> |
| In reply to | #1283374 |
Coresight ETMs are IP blocks used to perform HW assisted tracing
on a CPU core. This patch introduce the required auxiliary API
functions allowing the perf core to interact with a tracer.
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
MAINTAINERS | 3 +
tools/perf/arch/arm/util/Build | 2 +-
tools/perf/arch/arm/util/auxtrace.c | 48 ++++
tools/perf/arch/arm/util/cs_etm.c | 466 ++++++++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs_etm.h | 44 ++++
tools/perf/util/auxtrace.c | 1 +
tools/perf/util/auxtrace.h | 1 +
7 files changed, 564 insertions(+), 1 deletion(-)
create mode 100644 tools/perf/arch/arm/util/auxtrace.c
create mode 100644 tools/perf/arch/arm/util/cs_etm.c
create mode 100644 tools/perf/arch/arm/util/cs_etm.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 571a1dbe6bd1..cd2d3d7d41e6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1008,6 +1008,9 @@ F: Documentation/trace/coresight.txt
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: tools/perf/arch/arm/util/pmu.c
+F: tools/perf/arch/arm/util/auxtrace.c
+F: tools/perf/arch/arm/util/cs_etm.c
+F: tools/perf/arch/arm/util/cs_etm.h
ARM/CORGI MACHINE SUPPORT
M: Richard Purdie <rpurdie@rpsys.net>
diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build
index 66ab0b05549c..0a25a1248f42 100644
--- a/tools/perf/arch/arm/util/Build
+++ b/tools/perf/arch/arm/util/Build
@@ -3,4 +3,4 @@ libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LIBUNWIND) += unwind-libunwind.o
libperf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
-libperf-$(CONFIG_AUXTRACE) += pmu.o
+libperf-$(CONFIG_AUXTRACE) += pmu.o auxtrace.o cs_etm.o
diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c
new file mode 100644
index 000000000000..4988fdf7cb8a
--- /dev/null
+++ b/tools/perf/arch/arm/util/auxtrace.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdbool.h>
+#include <linux/coresight-pmu.h>
+
+#include "../../util/auxtrace.h"
+#include "../../util/evlist.h"
+#include "../../util/pmu.h"
+#include "cs_etm.h"
+
+struct auxtrace_record
+*auxtrace_record__init(struct perf_evlist *evlist, int *err)
+{
+ struct perf_pmu *cs_etm_pmu;
+ struct perf_evsel *evsel;
+ bool found_etm = false;
+
+ cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
+
+ if (evlist) {
+ evlist__for_each(evlist, evsel) {
+ if (cs_etm_pmu &&
+ evsel->attr.type == cs_etm_pmu->type)
+ found_etm = true;
+ }
+ }
+
+ if (found_etm)
+ return cs_etm_record_init(err);
+
+ *err = -EINVAL;
+ return NULL;
+}
diff --git a/tools/perf/arch/arm/util/cs_etm.c b/tools/perf/arch/arm/util/cs_etm.c
new file mode 100644
index 000000000000..5710b90e23d5
--- /dev/null
+++ b/tools/perf/arch/arm/util/cs_etm.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <api/fs/fs.h>
+#include <linux/bitops.h>
+#include <linux/coresight-pmu.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <linux/types.h>
+
+#include "../../perf.h"
+#include "../../util/auxtrace.h"
+#include "../../util/cpumap.h"
+#include "../../util/evlist.h"
+#include "../../util/pmu.h"
+#include "../../util/thread_map.h"
+#include "cs_etm.h"
+
+#include <stdlib.h>
+
+#define KiB(x) ((x) * 1024)
+#define MiB(x) ((x) * 1024 * 1024)
+
+struct cs_etm_recording {
+ struct auxtrace_record itr;
+ struct perf_pmu *cs_etm_pmu;
+ struct perf_evlist *evlist;
+ bool snapshot_mode;
+ size_t snapshot_size;
+};
+
+static int cs_etm_parse_snapshot_options(struct auxtrace_record *itr,
+ struct record_opts *opts,
+ const char *str)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ unsigned long long snapshot_size = 0;
+ char *endptr;
+
+ if (str) {
+ snapshot_size = strtoull(str, &endptr, 0);
+ if (*endptr || snapshot_size > SIZE_MAX)
+ return -1;
+ }
+
+ opts->auxtrace_snapshot_mode = true;
+ opts->auxtrace_snapshot_size = snapshot_size;
+ ptr->snapshot_size = snapshot_size;
+
+ return 0;
+}
+
+static int cs_etm_recording_options(struct auxtrace_record *itr,
+ struct perf_evlist *evlist,
+ struct record_opts *opts)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+ struct perf_evsel *evsel, *cs_etm_evsel = NULL;
+ const struct cpu_map *cpus = evlist->cpus;
+ bool privileged = (geteuid() == 0 || perf_event_paranoid() < 0);
+
+ ptr->evlist = evlist;
+ ptr->snapshot_mode = opts->auxtrace_snapshot_mode;
+
+ evlist__for_each(evlist, evsel) {
+ if (evsel->attr.type == cs_etm_pmu->type) {
+ if (cs_etm_evsel) {
+ pr_err("There may be only one %s event\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+ evsel->attr.freq = 0;
+ evsel->attr.sample_period = 1;
+ cs_etm_evsel = evsel;
+ opts->full_auxtrace = true;
+ }
+ }
+
+ /* no need to continue if at least one event of interest was found */
+ if (!cs_etm_evsel)
+ return 0;
+
+ if (opts->use_clockid) {
+ pr_err("Cannot use clockid (-k option) with %s\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+
+ /* we are in snapshot mode */
+ if (opts->auxtrace_snapshot_mode) {
+ /*
+ * No size were given to '-S' or '-m,', so go with
+ * the default
+ */
+ if (!opts->auxtrace_snapshot_size &&
+ !opts->auxtrace_mmap_pages) {
+ if (privileged) {
+ opts->auxtrace_mmap_pages = MiB(4) / page_size;
+ } else {
+ opts->auxtrace_mmap_pages =
+ KiB(128) / page_size;
+ if (opts->mmap_pages == UINT_MAX)
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+ } else if (!opts->auxtrace_mmap_pages && !privileged &&
+ opts->mmap_pages == UINT_MAX) {
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+
+ /*
+ * '-m,xyz' was specified but no snapshot size, so make the
+ * snapshot size as big as the auxtrace mmap area.
+ */
+ if (!opts->auxtrace_snapshot_size) {
+ opts->auxtrace_snapshot_size =
+ opts->auxtrace_mmap_pages * (size_t)page_size;
+ }
+
+ /*
+ * -Sxyz was specified but no auxtrace mmap area, so make the
+ * auxtrace mmap area big enough to fit the requested snapshot
+ * size.
+ */
+ if (!opts->auxtrace_mmap_pages) {
+ size_t sz = opts->auxtrace_snapshot_size;
+
+ sz = round_up(sz, page_size) / page_size;
+ opts->auxtrace_mmap_pages = roundup_pow_of_two(sz);
+ }
+
+ /* Snapshost size can't be bigger than the auxtrace area */
+ if (opts->auxtrace_snapshot_size >
+ opts->auxtrace_mmap_pages * (size_t)page_size) {
+ pr_err("Snapshot size %zu must not be greater than AUX area tracing mmap size %zu\n",
+ opts->auxtrace_snapshot_size,
+ opts->auxtrace_mmap_pages * (size_t)page_size);
+ return -EINVAL;
+ }
+
+ /* Something went wrong somewhere - this shouldn't happen */
+ if (!opts->auxtrace_snapshot_size ||
+ !opts->auxtrace_mmap_pages) {
+ pr_err("Failed to calculate default snapshot size and/or AUX area tracing mmap pages\n");
+ return -EINVAL;
+ }
+ }
+
+ /* We are in full trace mode but '-m,xyz' wasn't specified */
+ if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) {
+ if (privileged) {
+ opts->auxtrace_mmap_pages = MiB(4) / page_size;
+ } else {
+ opts->auxtrace_mmap_pages = KiB(128) / page_size;
+ if (opts->mmap_pages == UINT_MAX)
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+
+ }
+
+ /* Validate auxtrace_mmap_pages provided by user */
+ if (opts->auxtrace_mmap_pages) {
+ unsigned int max_page = (KiB(128) / page_size);
+ size_t sz = opts->auxtrace_mmap_pages * (size_t)page_size;
+
+ if (!privileged &&
+ opts->auxtrace_mmap_pages > max_page) {
+ opts->auxtrace_mmap_pages = max_page;
+ pr_err("auxtrace too big, truncating to %d\n",
+ max_page);
+ }
+
+ if (!is_power_of_2(sz)) {
+ pr_err("Invalid mmap size for %s: must be a power of 2\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+ }
+
+ if (opts->auxtrace_snapshot_mode)
+ pr_debug2("%s snapshot size: %zu\n", CORESIGHT_ETM_PMU_NAME,
+ opts->auxtrace_snapshot_size);
+
+ if (cs_etm_evsel) {
+ /*
+ * To obtain the auxtrace buffer file descriptor, the auxtrace
+ * event must come first.
+ */
+ perf_evlist__to_front(evlist, cs_etm_evsel);
+ /*
+ * In the case of per-cpu mmaps, we need the CPU on the
+ * AUX event.
+ */
+ if (!cpu_map__empty(cpus))
+ perf_evsel__set_sample_bit(cs_etm_evsel, CPU);
+ }
+
+ /* Add dummy event to keep tracking */
+ if (opts->full_auxtrace) {
+ struct perf_evsel *tracking_evsel;
+ int err;
+
+ err = parse_events(evlist, "dummy:u", NULL);
+ if (err)
+ return err;
+
+ tracking_evsel = perf_evlist__last(evlist);
+ perf_evlist__set_tracking_event(evlist, tracking_evsel);
+
+ tracking_evsel->attr.freq = 0;
+ tracking_evsel->attr.sample_period = 1;
+
+ /* In per-cpu case, always need the time of mmap events etc */
+ if (!cpu_map__empty(cpus))
+ perf_evsel__set_sample_bit(tracking_evsel, TIME);
+ }
+
+ return 0;
+}
+
+static u64 cs_etm_get_config(struct auxtrace_record *itr)
+{
+ u64 config = 0;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+ struct perf_evlist *evlist = ptr->evlist;
+ struct perf_evsel *evsel;
+
+ evlist__for_each(evlist, evsel) {
+ if (evsel->attr.type == cs_etm_pmu->type) {
+ /*
+ * Variable perf_event_attr::config is assigned to
+ * ETMv3/PTM. The bit fields have been made to match
+ * the ETMv3.5 ETRMCR register specification. See the
+ * PMU_FORMAT_ATTR() declarations in
+ * drivers/hwtracing/coresight/coresight-perf.c for
+ * details.
+ */
+ config = evsel->attr.config;
+ break;
+ }
+ }
+
+ return config;
+}
+
+static size_t
+cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
+ struct perf_evlist *evlist __maybe_unused)
+{
+ int records;
+ const struct cpu_map *cpus = evlist->cpus;
+
+ if (!cpu_map__empty(cpus)) {
+ records = cpu_map__nr(cpus);
+ goto out;
+ }
+
+ set_max_cpu_num();
+ records = cpu__max_cpu();
+out:
+ return records * CS_ETM_PRIV_SIZE;
+}
+
+static const char *metadata_etmv3_ro[CS_ETM_PRIV_MAX] = {
+ [CS_ETM_ETMCCER] = "mgmt/etmccer",
+ [CS_ETM_ETMIDR] = "mgmt/etmidr",
+};
+
+static int cs_etm_get_metadata(int cpu, int index,
+ struct auxtrace_record *itr,
+ struct auxtrace_info_event *info)
+{
+ char path[PATH_MAX];
+ int offset = 0, ret = 0;
+ int i, scan;
+ unsigned int val;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ offset = index * CS_ETM_PRIV_MAX;
+
+ /* Build generic header portion */
+ info->priv[offset + CS_ETM_MAGIC] = __perf_cs_etm_magic;
+ info->priv[offset + CS_ETM_CPU] = cpu;
+ info->priv[offset + CS_ETM_SNAPSHOT] = ptr->snapshot_mode;
+
+ /* Get user configurables from the session */
+ info->priv[offset + CS_ETM_ETMCR] = cs_etm_get_config(itr);
+ info->priv[offset + CS_ETM_ETMTRACEIDR] = coresight_get_trace_id(cpu);
+
+ /* Get RO metadata from sysfs */
+ for (i = CS_ETM_ETMCCER; i < CS_ETM_PRIV_MAX; i++) {
+ snprintf(path, PATH_MAX, "cpu%d/%s", cpu, metadata_etmv3_ro[i]);
+
+ scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
+ if (scan != 1) {
+ ret = -EINVAL;
+ break;
+ }
+
+ info->priv[offset + i] = val;
+ }
+
+ return ret;
+}
+
+static int cs_etm_info_fill(struct auxtrace_record *itr,
+ struct perf_session *session,
+ struct auxtrace_info_event *auxtrace_info,
+ size_t priv_size)
+{
+ int i, nr_cpu, ret = 0;
+ const struct cpu_map *cpus = session->evlist->cpus;
+
+ if (priv_size != cs_etm_info_priv_size(itr, session->evlist))
+ return -EINVAL;
+
+ if (!session->evlist->nr_mmaps)
+ return -EINVAL;
+
+ auxtrace_info->type = PERF_AUXTRACE_CS_ETM;
+
+ /* cpu map is not empty, we have specific CPUs to work with */
+ if (!cpu_map__empty(cpus)) {
+ for (i = 0; i < cpu_map__nr(cpus); i++) {
+ ret = cs_etm_get_metadata(cpus->map[i], i,
+ itr, auxtrace_info);
+ if (ret)
+ goto out;
+ }
+ } else {
+ /* get configuration for all CPUs in the system */
+ nr_cpu = cpu__max_cpu();
+ for (i = 0; i < nr_cpu; i++) {
+ ret = cs_etm_get_metadata(i, i, itr, auxtrace_info);
+ if (ret)
+ goto out;
+ }
+ }
+
+out:
+ return ret;
+}
+
+static int cs_etm_find_snapshot(struct auxtrace_record *itr __maybe_unused,
+ int idx, struct auxtrace_mmap *mm,
+ unsigned char *data __maybe_unused,
+ u64 *head, u64 *old)
+{
+ pr_debug3("%s: mmap index %d old head %zu new head %zu size %zu\n",
+ __func__, idx, (size_t)*old, (size_t)*head, mm->len);
+
+ *old = *head;
+ *head += mm->len;
+
+ return 0;
+}
+
+static int cs_etm_snapshot_start(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evlist__disable_event(ptr->evlist, evsel);
+ }
+ return -EINVAL;
+}
+
+static int cs_etm_snapshot_finish(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evlist__enable_event(ptr->evlist, evsel);
+ }
+ return -EINVAL;
+}
+
+static u64 cs_etm_reference(struct auxtrace_record *itr __maybe_unused)
+{
+ return (((u64) rand() << 0) & 0x00000000FFFFFFFFull) |
+ (((u64) rand() << 32) & 0xFFFFFFFF00000000ull);
+}
+
+static void cs_etm_recording_free(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ free(ptr);
+}
+
+static int cs_etm_read_finish(struct auxtrace_record *itr, int idx)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evlist__enable_event_idx(ptr->evlist,
+ evsel, idx);
+ }
+
+ return -EINVAL;
+}
+
+struct auxtrace_record *cs_etm_record_init(int *err)
+{
+ struct perf_pmu *cs_etm_pmu;
+ struct cs_etm_recording *ptr;
+
+ cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
+
+ if (!cs_etm_pmu) {
+ *err = -EINVAL;
+ goto out;
+ }
+
+ ptr = zalloc(sizeof(struct cs_etm_recording));
+ if (!ptr) {
+ *err = -ENOMEM;
+ goto out;
+ }
+
+ ptr->cs_etm_pmu = cs_etm_pmu;
+ ptr->itr.parse_snapshot_options = cs_etm_parse_snapshot_options;
+ ptr->itr.recording_options = cs_etm_recording_options;
+ ptr->itr.info_priv_size = cs_etm_info_priv_size;
+ ptr->itr.info_fill = cs_etm_info_fill;
+ ptr->itr.find_snapshot = cs_etm_find_snapshot;
+ ptr->itr.snapshot_start = cs_etm_snapshot_start;
+ ptr->itr.snapshot_finish = cs_etm_snapshot_finish;
+ ptr->itr.reference = cs_etm_reference;
+ ptr->itr.free = cs_etm_recording_free;
+ ptr->itr.read_finish = cs_etm_read_finish;
+
+ *err = 0;
+ return &ptr->itr;
+out:
+ return NULL;
+}
diff --git a/tools/perf/arch/arm/util/cs_etm.h b/tools/perf/arch/arm/util/cs_etm.h
new file mode 100644
index 000000000000..7e85c1b43598
--- /dev/null
+++ b/tools/perf/arch/arm/util/cs_etm.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDE__PERF_CS_ETM_H__
+#define INCLUDE__PERF_CS_ETM_H__
+
+/* Beginning of header common to both ETMv3 and V4 */
+enum {
+ CS_ETM_MAGIC,
+ CS_ETM_CPU,
+ CS_ETM_SNAPSHOT,
+};
+
+/* ETMv3/PTM metadata */
+enum {
+ /* Dynamic, configurable parameters */
+ CS_ETM_ETMCR = CS_ETM_SNAPSHOT + 1,
+ CS_ETM_ETMTRACEIDR,
+ /* RO, taken from sysFS */
+ CS_ETM_ETMCCER,
+ CS_ETM_ETMIDR,
+ CS_ETM_PRIV_MAX,
+};
+
+static const u64 __perf_cs_etm_magic = 0x3030303030303030ULL;
+#define CS_ETM_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
+
+struct auxtrace_record *cs_etm_record_init(int *err);
+
+#endif
diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c
index cc1c9ce5cc56..a6f291dbc4d9 100644
--- a/tools/perf/util/auxtrace.c
+++ b/tools/perf/util/auxtrace.c
@@ -892,6 +892,7 @@ int perf_event__process_auxtrace_info(struct perf_tool *tool __maybe_unused,
return intel_pt_process_auxtrace_info(event, session);
case PERF_AUXTRACE_INTEL_BTS:
return intel_bts_process_auxtrace_info(event, session);
+ case PERF_AUXTRACE_CS_ETM:
case PERF_AUXTRACE_UNKNOWN:
default:
return -EINVAL;
diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h
index e5a8e2d4f2af..adb53e7bcabf 100644
--- a/tools/perf/util/auxtrace.h
+++ b/tools/perf/util/auxtrace.h
@@ -41,6 +41,7 @@ enum auxtrace_type {
PERF_AUXTRACE_UNKNOWN,
PERF_AUXTRACE_INTEL_PT,
PERF_AUXTRACE_INTEL_BTS,
+ PERF_AUXTRACE_CS_ETM,
};
enum itrace_period_type {
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 08/26] coresight: etm3x: adding operation mode for etm_enable() |
| Message-ID | <qBJsd-1YU-1@gated-at.bofh.it> |
| In reply to | #1283374 |
Adding a new mode to source API enable() in order to
distinguish where the request comes from. That way it is
possible to perform different operations based on where
the request was issued from.
The ETM4x driver is also modified to keep in sync with the
new interface.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm.h | 5 +-
.../hwtracing/coresight/coresight-etm3x-sysfs.c | 4 +-
drivers/hwtracing/coresight/coresight-etm3x.c | 68 +++++++++++++++++++---
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
drivers/hwtracing/coresight/coresight-priv.h | 6 ++
drivers/hwtracing/coresight/coresight.c | 6 +-
include/linux/coresight.h | 2 +-
7 files changed, 76 insertions(+), 17 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index 9317510d555f..a8663780a908 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -13,6 +13,7 @@
#ifndef _CORESIGHT_CORESIGHT_ETM_H
#define _CORESIGHT_CORESIGHT_ETM_H
+#include <asm/local.h>
#include <linux/spinlock.h>
#include "coresight-priv.h"
@@ -214,7 +215,7 @@ struct etm_config {
* @port_size: port size as reported by ETMCR bit 4-6 and 21.
* @arch: ETM/PTM version number.
* @use_cpu14: true if management registers need to be accessed via CP14.
- * @enable: is this ETM/PTM currently tracing.
+ * @mode: this tracer's mode, i.e sysFS, Perf or disabled.
* @sticky_enable: true if ETM base configuration has been done.
* @boot_enable:true if we should start tracing at boot time.
* @os_unlock: true if access to management registers is allowed.
@@ -238,7 +239,7 @@ struct etm_drvdata {
int port_size;
u8 arch;
bool use_cp14;
- bool enable;
+ local_t mode;
bool sticky_enable;
bool boot_enable;
bool os_unlock;
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index 410d29e2b90c..6da50d94ec6f 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -811,7 +811,7 @@ static ssize_t cntr_val_show(struct device *dev,
if (WARN_ON_ONCE(!config))
return -EINVAL;
- if (!drvdata->enable) {
+ if (!local_read(&drvdata->mode)) {
spin_lock(&drvdata->spinlock);
for (i = 0; i < drvdata->nr_cntr; i++)
ret += sprintf(buf, "counter %d: %x\n",
@@ -1072,7 +1072,7 @@ static ssize_t seq_curr_state_show(struct device *dev,
if (WARN_ON_ONCE(!config))
return -EINVAL;
- if (!drvdata->enable) {
+ if (!local_read(&drvdata->mode)) {
val = config->seq_curr_state;
goto out;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index d0337776e9b9..0035953a1102 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -327,7 +327,7 @@ int etm_get_trace_id(struct etm_drvdata *drvdata)
if (!drvdata)
goto out;
- if (!drvdata->enable)
+ if (!local_read(&drvdata->mode))
return drvdata->traceid;
pm_runtime_get_sync(drvdata->dev);
@@ -353,7 +353,7 @@ static int etm_trace_id(struct coresight_device *csdev)
return etm_get_trace_id(drvdata);
}
-static int etm_enable(struct coresight_device *csdev)
+static int etm_enable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
int ret;
@@ -372,18 +372,44 @@ static int etm_enable(struct coresight_device *csdev)
goto err;
}
- drvdata->enable = true;
drvdata->sticky_enable = true;
-
spin_unlock(&drvdata->spinlock);
dev_info(drvdata->dev, "ETM tracing enabled\n");
return 0;
+
err:
spin_unlock(&drvdata->spinlock);
return ret;
}
+static int etm_enable(struct coresight_device *csdev, u32 mode)
+{
+ int ret;
+ u32 val;
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
+
+ /* Someone is already using the tracer */
+ if (val)
+ return -EBUSY;
+
+ switch (mode) {
+ case CS_MODE_SYSFS:
+ ret = etm_enable_sysfs(csdev);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ /* The tracer didn't start */
+ if (ret)
+ local_set(&drvdata->mode, CS_MODE_DISABLED);
+
+ return ret;
+}
+
static void etm_disable_hw(void *info)
{
int i;
@@ -414,7 +440,7 @@ static void etm_disable_hw(void *info)
dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
}
-static void etm_disable(struct coresight_device *csdev)
+static void etm_disable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etm_config *config = get_etm_config(drvdata);
@@ -433,7 +459,6 @@ static void etm_disable(struct coresight_device *csdev)
* ensures that register writes occur when cpu is powered.
*/
smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
- drvdata->enable = false;
kfree(config);
spin_unlock(&drvdata->spinlock);
@@ -442,6 +467,33 @@ static void etm_disable(struct coresight_device *csdev)
dev_info(drvdata->dev, "ETM tracing disabled\n");
}
+static void etm_disable(struct coresight_device *csdev)
+{
+ u32 mode;
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ /*
+ * For as long as the tracer isn't disabled another entity can't
+ * change its status. As such we can read the status here without
+ * fearing it will change under us.
+ */
+ mode = local_read(&drvdata->mode);
+
+ switch (mode) {
+ case CS_MODE_DISABLED:
+ break;
+ case CS_MODE_SYSFS:
+ etm_disable_sysfs(csdev);
+ break;
+ default:
+ WARN_ON_ONCE(mode);
+ return;
+ }
+
+ if (mode)
+ local_set(&drvdata->mode, CS_MODE_DISABLED);
+}
+
static const struct coresight_ops_source etm_source_ops = {
.cpu_id = etm_cpu_id,
.trace_id = etm_trace_id,
@@ -469,7 +521,7 @@ static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
etmdrvdata[cpu]->os_unlock = true;
}
- if (etmdrvdata[cpu]->enable)
+ if (local_read(&etmdrvdata[cpu]->mode))
etm_enable_hw(etmdrvdata[cpu]);
spin_unlock(&etmdrvdata[cpu]->spinlock);
break;
@@ -482,7 +534,7 @@ static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
case CPU_DYING:
spin_lock(&etmdrvdata[cpu]->spinlock);
- if (etmdrvdata[cpu]->enable)
+ if (local_read(&etmdrvdata[cpu]->mode))
etm_disable_hw(etmdrvdata[cpu]);
spin_unlock(&etmdrvdata[cpu]->spinlock);
break;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 1c6e32dd6e49..4ab291b3a6c8 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -180,7 +180,7 @@ static void etm4_enable_hw(void *info)
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
}
-static int etm4_enable(struct coresight_device *csdev)
+static int etm4_enable(struct coresight_device *csdev, u32 mode)
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
int ret;
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 7b193a34d709..2dc59a5c5b1e 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -34,6 +34,12 @@
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
+enum cs_mode {
+ CS_MODE_DISABLED,
+ CS_MODE_SYSFS,
+ CS_MODE_PERF,
+};
+
static inline void CS_LOCK(void __iomem *addr)
{
do {
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index e63e42410ad2..4e326d792100 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -222,7 +222,7 @@ static void coresight_disable_link(struct coresight_device *csdev,
csdev->enable = false;
}
-static int coresight_enable_source(struct coresight_device *csdev)
+static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
{
int ret;
@@ -234,7 +234,7 @@ static int coresight_enable_source(struct coresight_device *csdev)
if (!csdev->enable) {
if (source_ops(csdev)->enable) {
- ret = source_ops(csdev)->enable(csdev);
+ ret = source_ops(csdev)->enable(csdev, mode);
if (ret)
return ret;
}
@@ -443,7 +443,7 @@ int coresight_enable(struct coresight_device *csdev)
if (ret)
goto err_path;
- ret = coresight_enable_source(csdev);
+ ret = coresight_enable_source(csdev, CS_MODE_SYSFS);
if (ret)
goto err_source;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 851ecb22397e..61dfb8d511ea 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -213,7 +213,7 @@ struct coresight_ops_link {
struct coresight_ops_source {
int (*cpu_id)(struct coresight_device *csdev);
int (*trace_id)(struct coresight_device *csdev);
- int (*enable)(struct coresight_device *csdev);
+ int (*enable)(struct coresight_device *csdev, u32 mode);
void (*disable)(struct coresight_device *csdev);
};
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 11/26] coresight: etm3x: changing default trace configuration |
| Message-ID | <qBJsd-1YU-3@gated-at.bofh.it> |
| In reply to | #1283374 |
Changing default configuration to include the entire address
range rather than just the kernel. That way traces are more
inclusive and it is easier to narrow down if needed.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm.h | 2 ++
drivers/hwtracing/coresight/coresight-etm3x.c | 29 ++++++++++++---------------
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index a8663780a908..f01862fc98dd 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -146,6 +146,7 @@
* @startstop_ctrl: setting for register ETMTSSCR.
* @enable_event: setting for register ETMTEEVR.
* @enable_ctrl1: setting for register ETMTECR1.
+ * @enable_ctrl2: setting for register ETMTECR2.
* @fifofull_level: setting for register ETMFFLR.
* @addr_idx: index for the address comparator selection.
* @addr_val: value for address comparator register.
@@ -179,6 +180,7 @@ struct etm_config {
u32 startstop_ctrl;
u32 enable_event;
u32 enable_ctrl1;
+ u32 enable_ctrl2;
u32 fifofull_level;
u8 addr_idx;
u32 addr_val[ETM_MAX_ADDR_CMP];
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index a0252ffb4ba7..cfaf8e840bd6 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -608,26 +608,23 @@ static void etm_init_arch_data(void *info)
static void etm_init_default_data(struct etm_config *config)
{
- u32 flags = (1 << 0 | /* instruction execute*/
- 3 << 3 | /* ARM instruction */
- 0 << 5 | /* No data value comparison */
- 0 << 7 | /* No exact mach */
- 0 << 8 | /* Ignore context ID */
- 0 << 10); /* Security ignored */
-
if (WARN_ON_ONCE(!config))
return;
- config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
- config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
- config->addr_val[0] = (u32) _stext;
- config->addr_val[1] = (u32) _etext;
- config->addr_acctype[0] = flags;
- config->addr_acctype[1] = flags;
- config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
- config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
-
etm_set_default(config);
+
+ /*
+ * Taken verbatim from the TRM:
+ *
+ * To trace all memory:
+ * set bit [24] in register 0x009, the ETMTECR1, to 1
+ * set all other bits in register 0x009, the ETMTECR1, to 0
+ * set all bits in register 0x007, the ETMTECR2, to 0
+ * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
+ */
+ config->enable_ctrl1 = BIT(24);
+ config->enable_ctrl2 = 0x0;
+ config->enable_event = ETM_HARD_WIRE_RES_A;
}
static void etm_init_trace_id(struct etm_drvdata *drvdata)
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 18/26] coresight: etb10: implementing AUX space API |
| Message-ID | <qBJsd-1YU-5@gated-at.bofh.it> |
| In reply to | #1283374 |
Adding an ETB10 specific AUX area operations to be used
by the perf framework when events are initialised.
Part of this operation involves modeling the mmap'ed area
based on the specific ways a sink buffer gathers information.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 237 ++++++++++++++++++++++++++
include/linux/coresight.h | 22 ++-
2 files changed, 257 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index dc4d707b28aa..79c87f42c550 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -28,6 +28,11 @@
#include <linux/coresight.h>
#include <linux/amba/bus.h>
#include <linux/clk.h>
+#include <linux/circ_buf.h>
+#include <linux/mm.h>
+#include <linux/perf_event.h>
+
+#include <asm/local.h>
#include "coresight-priv.h"
@@ -65,6 +70,26 @@
#define ETB_FRAME_SIZE_WORDS 4
/**
+ * struct cs_buffer - keep track of a recording session' specifics
+ * @cur: index of the current buffer
+ * @nr_pages: max number of pages granted to us
+ * @offset: offset within the current buffer
+ * @data_size: how much we collected in this run
+ * @lost: other than zero if we had a HW buffer wrap around
+ * @snapshot: is this run in snapshot mode
+ * @data_pages: a handle the ring buffer
+ */
+struct cs_buffers {
+ unsigned int cur;
+ unsigned int nr_pages;
+ unsigned long offset;
+ local_t data_size;
+ local_t lost;
+ bool snapshot;
+ void **data_pages;
+};
+
+/**
* struct etb_drvdata - specifics associated to an ETB component
* @base: memory mapped base address for this component.
* @dev: the device entity associated to this component.
@@ -266,9 +291,221 @@ static void etb_disable(struct coresight_device *csdev)
dev_info(drvdata->dev, "ETB disabled\n");
}
+static void *etb_get_config(struct coresight_device *csdev, int cpu,
+ void **pages, int nr_pages, bool overwrite)
+{
+ int node;
+ struct cs_buffers *buf;
+
+ if (cpu == -1)
+ cpu = smp_processor_id();
+ node = cpu_to_node(cpu);
+
+ buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
+ if (!buf)
+ return NULL;
+
+ buf->snapshot = overwrite;
+ buf->nr_pages = nr_pages;
+ buf->data_pages = pages;
+
+ return buf;
+}
+
+static void etb_put_config(void *config)
+{
+ struct cs_buffers *buf = config;
+
+ kfree(buf);
+}
+
+static int etb_set_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config)
+{
+ int ret = 0;
+ unsigned long head;
+ struct cs_buffers *buf = sink_config;
+
+ /* wrap head around to the amount of space we have */
+ head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
+
+ /* find the page to write to */
+ buf->cur = head / PAGE_SIZE;
+
+ /* and offset within that page */
+ buf->offset = head % PAGE_SIZE;
+
+ local_set(&buf->data_size, 0);
+
+ return ret;
+}
+
+static unsigned long etb_reset_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config, bool *lost)
+{
+ unsigned long size = 0;
+ struct cs_buffers *buf = sink_config;
+
+ if (buf) {
+ /*
+ * In snapshot mode ->data_size holds the new address of the
+ * ring buffer's head. The size itself is the whole address
+ * range since we want the latest information.
+ */
+ if (buf->snapshot)
+ handle->head = local_xchg(&buf->data_size,
+ buf->nr_pages << PAGE_SHIFT);
+
+ /*
+ * Tell the tracer PMU how much we got in this run and if
+ * something went wrong along the way. Nobody else can use
+ * this cs_buffers instance until we are done. As such
+ * resetting parameters here and squaring off with the ring
+ * buffer API in the tracer PMU is fine.
+ */
+ *lost = local_xchg(&buf->lost, 0);
+ size = local_xchg(&buf->data_size, 0);
+ }
+
+ return size;
+}
+
+static void etb_update_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config)
+{
+ int i, cur;
+ u8 *buf_ptr;
+ u32 read_ptr, write_ptr, capacity;
+ u32 status, read_data, to_read;
+ unsigned long flags, offset;
+ struct cs_buffers *buf = sink_config;
+ struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ if (!buf)
+ return;
+
+ capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
+
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+
+ CS_UNLOCK(drvdata->base);
+ etb_disable_hw(drvdata);
+
+ /* unit is in words, not bytes */
+ read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
+ write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
+
+ /*
+ * Entries should be aligned to the frame size. If they are not
+ * go back to the last alignement point to give decoding tools a
+ * chance to fix things.
+ */
+ if (write_ptr % ETB_FRAME_SIZE_WORDS) {
+ dev_err(drvdata->dev,
+ "write_ptr: %lu not aligned to formatter frame size\n",
+ (unsigned long)write_ptr);
+
+ write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
+ local_inc(&buf->lost);
+ }
+
+ /*
+ * Get a hold of the status register and see if a wrap around
+ * has occurred. If so adjust things accordingly. Otherwise
+ * start at the beginning and go until the write pointer has
+ * been reached.
+ */
+ status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
+ if (status & ETB_STATUS_RAM_FULL) {
+ local_inc(&buf->lost);
+ to_read = capacity;
+ read_ptr = write_ptr;
+ } else {
+ to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth);
+ to_read *= ETB_FRAME_SIZE_WORDS;
+ }
+
+ /*
+ * Make sure we don't overwrite data that hasn't been consumed yet.
+ * It is entirely possible that the HW buffer has more data than the
+ * ring buffer can currently handle. If so adjust the start address
+ * to take only the last traces.
+ *
+ * In snapshot mode we are looking to get the latest traces only and as
+ * such, we don't care about not overwriting data that hasn't been
+ * processed by user space.
+ */
+ if (!buf->snapshot && to_read > handle->size) {
+ u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1);
+
+ /* The new read pointer must be frame size aligned */
+ to_read -= handle->size & mask;
+ /*
+ * Move the RAM read pointer up, keeping in mind that
+ * everything is in frame size units.
+ */
+ read_ptr = (write_ptr + drvdata->buffer_depth) -
+ to_read / ETB_FRAME_SIZE_WORDS;
+ /* Wrap around if need be*/
+ read_ptr &= ~(drvdata->buffer_depth - 1);
+ /* let the decoder know we've skipped ahead */
+ local_inc(&buf->lost);
+ }
+
+ /* finally tell HW where we want to start reading from */
+ writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
+
+ cur = buf->cur;
+ offset = buf->offset;
+ for (i = 0; i < to_read; i += 4) {
+ buf_ptr = buf->data_pages[cur] + offset;
+ read_data = readl_relaxed(drvdata->base +
+ ETB_RAM_READ_DATA_REG);
+ *buf_ptr++ = read_data >> 0;
+ *buf_ptr++ = read_data >> 8;
+ *buf_ptr++ = read_data >> 16;
+ *buf_ptr++ = read_data >> 24;
+
+ offset += 4;
+ if (offset >= PAGE_SIZE) {
+ offset = 0;
+ cur++;
+ /* wrap around at the end of the buffer */
+ cur &= buf->nr_pages - 1;
+ }
+ }
+
+ /* reset ETB buffer for next run */
+ writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
+ writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
+
+ /*
+ * In snapshot mode all we have to do is communicate to
+ * perf_aux_output_end() the address of the current head. In full
+ * trace mode the same function expects a size to move rb->aux_head
+ * forward.
+ */
+ if (buf->snapshot)
+ local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
+ else
+ local_add(to_read, &buf->data_size);
+
+ etb_enable_hw(drvdata);
+ CS_LOCK(drvdata->base);
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+}
+
static const struct coresight_ops_sink etb_sink_ops = {
.enable = etb_enable,
.disable = etb_disable,
+ .get_config = etb_get_config,
+ .put_config = etb_put_config,
+ .set_buffer = etb_set_buffer,
+ .reset_buffer = etb_reset_buffer,
+ .update_buffer = etb_update_buffer,
};
static const struct coresight_ops etb_cs_ops = {
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 2b94994d2c02..12af12f54173 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -14,6 +14,7 @@
#define _LINUX_CORESIGHT_H
#include <linux/device.h>
+#include <linux/perf_event.h>
#include <linux/sched.h>
/* Peripheral id registers (0xFD0-0xFEC) */
@@ -181,12 +182,29 @@ struct coresight_device {
/**
* struct coresight_ops_sink - basic operations for a sink
* Operations available for sinks
- * @enable: enables the sink.
- * @disable: disables the sink.
+ * @enable: enables the sink.
+ * @disable: disables the sink.
+ * @get_config: initialises perf's ring buffer for trace collection.
+ * @put_config: release memory allocated in @get_config.
+ * @set_buffer: initialises buffer mechanic before a trace session.
+ * @reset_buffer: finalises buffer mechanic after a trace session.
+ * @update_buffer: update buffer pointers after a trace session.
*/
struct coresight_ops_sink {
int (*enable)(struct coresight_device *csdev, u32 mode);
void (*disable)(struct coresight_device *csdev);
+ void *(*get_config)(struct coresight_device *csdev, int cpu,
+ void **pages, int nr_pages, bool overwrite);
+ void (*put_config)(void *config);
+ int (*set_buffer)(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config);
+ unsigned long (*reset_buffer)(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config, bool *lost);
+ void (*update_buffer)(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config);
};
/**
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Alexander Shishkin <alexander.shishkin@linux.intel.com> |
|---|---|
| Date | 2015-12-11 15:10 +0100 |
| Subject | Re: [PATCH V6 18/26] coresight: etb10: implementing AUX space API |
| Message-ID | <qEwyv-5wq-35@gated-at.bofh.it> |
| In reply to | #1283378 |
Mathieu Poirier <mathieu.poirier@linaro.org> writes:
> +static void *etb_get_config(struct coresight_device *csdev, int cpu,
> + void **pages, int nr_pages, bool overwrite)
> +{
> + int node;
> + struct cs_buffers *buf;
> +
> + if (cpu == -1)
> + cpu = smp_processor_id();
> + node = cpu_to_node(cpu);
> +
> + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
> + if (!buf)
> + return NULL;
> +
> + buf->snapshot = overwrite;
> + buf->nr_pages = nr_pages;
> + buf->data_pages = pages;
> +
> + return buf;
> +}
Nitpick: why is this called "get_config"? I was just looking for
something else and noticed that both sources and sinks have
.get_config() callback (I was looking for the source's one), but this
guy doesn't seem to be getting any config, but rather allocating a
buffer descriptor.
Regards,
--
Alex
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-11 22:20 +0100 |
| Subject | Re: [PATCH V6 18/26] coresight: etb10: implementing AUX space API |
| Message-ID | <qEDgC-1n0-21@gated-at.bofh.it> |
| In reply to | #1289604 |
On 11 December 2015 at 07:00, Alexander Shishkin
<alexander.shishkin@linux.intel.com> wrote:
> Mathieu Poirier <mathieu.poirier@linaro.org> writes:
>
>> +static void *etb_get_config(struct coresight_device *csdev, int cpu,
>> + void **pages, int nr_pages, bool overwrite)
>> +{
>> + int node;
>> + struct cs_buffers *buf;
>> +
>> + if (cpu == -1)
>> + cpu = smp_processor_id();
>> + node = cpu_to_node(cpu);
>> +
>> + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
>> + if (!buf)
>> + return NULL;
>> +
>> + buf->snapshot = overwrite;
>> + buf->nr_pages = nr_pages;
>> + buf->data_pages = pages;
>> +
>> + return buf;
>> +}
>
> Nitpick: why is this called "get_config"? I was just looking for
> something else and noticed that both sources and sinks have
> .get_config() callback (I was looking for the source's one), but this
> guy doesn't seem to be getting any config, but rather allocating a
> buffer descriptor.
My goal was to harmonise the naming convention between source and
sinks as much as possible, and I'm still not quite sure how to call
that function... Given the end result something like
"etb_alloc_buffer" would likely be more appropriate.
>
> Regards,
> --
> Alex
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 03/26] coresight: etm3x: unlocking tracers in default arch init |
| Message-ID | <qBJse-1YU-11@gated-at.bofh.it> |
| In reply to | #1283374 |
Calling function 'smp_call_function_single()' to unlock a
tracer and calling it again right after to perform the
default initialisation doesn't make sense.
Moving 'etm_os_unlock()' just before making the default
initialisation results in the same outcome while saving
one call to 'smp_call_function_single()'.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm3x.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index 2a1950d0753d..737b6164f4a5 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -47,11 +47,11 @@ static struct etm_drvdata *etmdrvdata[NR_CPUS];
* and OS lock must be unlocked before any memory mapped access on such
* processors, otherwise memory mapped reads/writes will be invalid.
*/
-static void etm_os_unlock(void *info)
+static void etm_os_unlock(struct etm_drvdata *drvdata)
{
- struct etm_drvdata *drvdata = (struct etm_drvdata *)info;
/* Writing any value to ETMOSLAR unlocks the trace registers */
etm_writel(drvdata, 0x0, ETMOSLAR);
+ drvdata->os_unlock = true;
isb();
}
@@ -478,6 +478,9 @@ static void etm_init_arch_data(void *info)
u32 etmccr;
struct etm_drvdata *drvdata = info;
+ /* Make sure all registers are accessible */
+ etm_os_unlock(drvdata);
+
CS_UNLOCK(drvdata->base);
/* First dummy read */
@@ -602,9 +605,6 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
get_online_cpus();
etmdrvdata[drvdata->cpu] = drvdata;
- if (!smp_call_function_single(drvdata->cpu, etm_os_unlock, drvdata, 1))
- drvdata->os_unlock = true;
-
if (smp_call_function_single(drvdata->cpu,
etm_init_arch_data, drvdata, 1))
dev_err(dev, "ETM arch init failed\n");
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 07/26] coresight: moving PM runtime operations to core framework |
| Message-ID | <qBJse-1YU-17@gated-at.bofh.it> |
| In reply to | #1283374 |
Moving PM runtime operations in Coresight devices enable() and
disable() API to the framework core when a path is setup. That
way the runtime core doesn't have to be involved everytime a
path is enabled. It also avoids calling runtime PM operations
in IRQ context.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 4 ----
drivers/hwtracing/coresight/coresight-etm3x.c | 3 ---
drivers/hwtracing/coresight/coresight-etm4x.c | 6 ------
drivers/hwtracing/coresight/coresight-funnel.c | 2 --
drivers/hwtracing/coresight/coresight-replicator-qcom.c | 4 ----
drivers/hwtracing/coresight/coresight-replicator.c | 2 --
drivers/hwtracing/coresight/coresight-tmc.c | 5 -----
drivers/hwtracing/coresight/coresight-tpiu.c | 2 --
drivers/hwtracing/coresight/coresight.c | 9 ++++++++-
9 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 77d0f9c1118d..1301edc44629 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -137,8 +137,6 @@ static int etb_enable(struct coresight_device *csdev)
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
unsigned long flags;
- pm_runtime_get_sync(drvdata->dev);
-
spin_lock_irqsave(&drvdata->spinlock, flags);
etb_enable_hw(drvdata);
drvdata->enable = true;
@@ -247,8 +245,6 @@ static void etb_disable(struct coresight_device *csdev)
drvdata->enable = false;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- pm_runtime_put(drvdata->dev);
-
dev_info(drvdata->dev, "ETB disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index 9dd88cf8f15c..d0337776e9b9 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -358,7 +358,6 @@ static int etm_enable(struct coresight_device *csdev)
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
int ret;
- pm_runtime_get_sync(csdev->dev.parent);
spin_lock(&drvdata->spinlock);
/*
@@ -382,7 +381,6 @@ static int etm_enable(struct coresight_device *csdev)
return 0;
err:
spin_unlock(&drvdata->spinlock);
- pm_runtime_put(csdev->dev.parent);
return ret;
}
@@ -440,7 +438,6 @@ static void etm_disable(struct coresight_device *csdev)
spin_unlock(&drvdata->spinlock);
put_online_cpus();
- pm_runtime_put(csdev->dev.parent);
dev_info(drvdata->dev, "ETM tracing disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index a6707642bb23..1c6e32dd6e49 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -72,7 +72,6 @@ static int etm4_trace_id(struct coresight_device *csdev)
if (!drvdata->enable)
return drvdata->trcid;
- pm_runtime_get_sync(drvdata->dev);
spin_lock_irqsave(&drvdata->spinlock, flags);
CS_UNLOCK(drvdata->base);
@@ -81,7 +80,6 @@ static int etm4_trace_id(struct coresight_device *csdev)
CS_LOCK(drvdata->base);
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- pm_runtime_put(drvdata->dev);
return trace_id;
}
@@ -187,7 +185,6 @@ static int etm4_enable(struct coresight_device *csdev)
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
int ret;
- pm_runtime_get_sync(drvdata->dev);
spin_lock(&drvdata->spinlock);
/*
@@ -207,7 +204,6 @@ static int etm4_enable(struct coresight_device *csdev)
return 0;
err:
spin_unlock(&drvdata->spinlock);
- pm_runtime_put(drvdata->dev);
return ret;
}
@@ -256,8 +252,6 @@ static void etm4_disable(struct coresight_device *csdev)
spin_unlock(&drvdata->spinlock);
put_online_cpus();
- pm_runtime_put(drvdata->dev);
-
dev_info(drvdata->dev, "ETM tracing disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 2e36bde7fcb4..a47bba361833 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -69,7 +69,6 @@ static int funnel_enable(struct coresight_device *csdev, int inport,
{
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- pm_runtime_get_sync(drvdata->dev);
funnel_enable_hw(drvdata, inport);
dev_info(drvdata->dev, "FUNNEL inport %d enabled\n", inport);
@@ -95,7 +94,6 @@ static void funnel_disable(struct coresight_device *csdev, int inport,
struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
funnel_disable_hw(drvdata, inport);
- pm_runtime_put(drvdata->dev);
dev_info(drvdata->dev, "FUNNEL inport %d disabled\n", inport);
}
diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
index 584059e9e866..8149087e8966 100644
--- a/drivers/hwtracing/coresight/coresight-replicator-qcom.c
+++ b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
@@ -48,8 +48,6 @@ static int replicator_enable(struct coresight_device *csdev, int inport,
{
struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent);
- pm_runtime_get_sync(drvdata->dev);
-
CS_UNLOCK(drvdata->base);
/*
@@ -86,8 +84,6 @@ static void replicator_disable(struct coresight_device *csdev, int inport,
CS_LOCK(drvdata->base);
- pm_runtime_put(drvdata->dev);
-
dev_info(drvdata->dev, "REPLICATOR disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index 963ac197c253..a0fbb2e05389 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -41,7 +41,6 @@ static int replicator_enable(struct coresight_device *csdev, int inport,
{
struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- pm_runtime_get_sync(drvdata->dev);
dev_info(drvdata->dev, "REPLICATOR enabled\n");
return 0;
}
@@ -51,7 +50,6 @@ static void replicator_disable(struct coresight_device *csdev, int inport,
{
struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- pm_runtime_put(drvdata->dev);
dev_info(drvdata->dev, "REPLICATOR disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index a57c7ec1661f..5e2a71767870 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -242,12 +242,9 @@ static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
{
unsigned long flags;
- pm_runtime_get_sync(drvdata->dev);
-
spin_lock_irqsave(&drvdata->spinlock, flags);
if (drvdata->reading) {
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- pm_runtime_put(drvdata->dev);
return -EBUSY;
}
@@ -381,8 +378,6 @@ out:
drvdata->enable = false;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
- pm_runtime_put(drvdata->dev);
-
dev_info(drvdata->dev, "TMC disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
index 7214efd10db5..e19b86e61c38 100644
--- a/drivers/hwtracing/coresight/coresight-tpiu.c
+++ b/drivers/hwtracing/coresight/coresight-tpiu.c
@@ -74,7 +74,6 @@ static int tpiu_enable(struct coresight_device *csdev)
{
struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- pm_runtime_get_sync(csdev->dev.parent);
tpiu_enable_hw(drvdata);
dev_info(drvdata->dev, "TPIU enabled\n");
@@ -98,7 +97,6 @@ static void tpiu_disable(struct coresight_device *csdev)
struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
tpiu_disable_hw(drvdata);
- pm_runtime_put(csdev->dev.parent);
dev_info(drvdata->dev, "TPIU disabled\n");
}
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 74beba461aa2..e63e42410ad2 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -24,6 +24,7 @@
#include <linux/coresight.h>
#include <linux/of_platform.h>
#include <linux/delay.h>
+#include <linux/pm_runtime.h>
#include "coresight-priv.h"
@@ -361,7 +362,8 @@ out:
/*
* A path from this element to a sink has been found. The elements
* leading to the sink are already enqueued, all that is left to do
- * is add a node for this element.
+ * is tell the PM runtime core we need this element and add a node
+ * for it.
*/
node = kzalloc(sizeof(struct coresight_node), GFP_KERNEL);
if (!node)
@@ -369,6 +371,7 @@ out:
node->csdev = csdev;
list_add(&node->link, path);
+ pm_runtime_get_sync(csdev->dev.parent);
return 0;
}
@@ -400,9 +403,13 @@ struct list_head *coresight_build_path(struct coresight_device *csdev)
*/
void coresight_release_path(struct list_head *path)
{
+ struct coresight_device *csdev;
struct coresight_node *nd, *next;
list_for_each_entry_safe(nd, next, path, link) {
+ csdev = nd->csdev;
+
+ pm_runtime_put_sync(csdev->dev.parent);
list_del(&nd->link);
kfree(nd);
}
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 05/26] coresight: etm3x: implementing 'cpu_id()' API |
| Message-ID | <qBJse-1YU-7@gated-at.bofh.it> |
| In reply to | #1283374 |
Other than plainly parsing the device tree there is no way to
know which CPU a tracer is affined to. As such adding an
interface to lookup the CPU field enclosed in the etm_drvdata
structure that was initialised at boot time.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm3x.c | 8 ++++++++
include/linux/coresight.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index b30add73c0ae..9dd88cf8f15c 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -312,6 +312,13 @@ static void etm_enable_hw(void *info)
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
}
+static int etm_cpu_id(struct coresight_device *csdev)
+{
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ return drvdata->cpu;
+}
+
int etm_get_trace_id(struct etm_drvdata *drvdata)
{
unsigned long flags;
@@ -439,6 +446,7 @@ static void etm_disable(struct coresight_device *csdev)
}
static const struct coresight_ops_source etm_source_ops = {
+ .cpu_id = etm_cpu_id,
.trace_id = etm_trace_id,
.enable = etm_enable,
.disable = etm_disable,
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index a7cabfa23b55..bf62b265bf52 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -205,12 +205,15 @@ struct coresight_ops_link {
/**
* struct coresight_ops_source - basic operations for a source
* Operations available for sources.
+ * @cpu_id: returns the value of the CPU number this component
+ * is associated to.
* @trace_id: returns the value of the component's trace ID as known
to the HW.
* @enable: enables tracing for a source.
* @disable: disables tracing for a source.
*/
struct coresight_ops_source {
+ int (*cpu_id)(struct coresight_device *csdev);
int (*trace_id)(struct coresight_device *csdev);
int (*enable)(struct coresight_device *csdev);
void (*disable)(struct coresight_device *csdev);
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 09/26] coresight: add API to get sink from path |
| Message-ID | <qBJse-1YU-23@gated-at.bofh.it> |
| In reply to | #1283374 |
Add an API allowing external code to quickly get a handle on the
sink within a path. The sink is always last, but adding an API allows
to keep the path's node structure private and remove redundant checks.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-priv.h | 1 +
drivers/hwtracing/coresight/coresight.c | 15 +++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 2dc59a5c5b1e..ed116b303e87 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -60,6 +60,7 @@ static inline void CS_UNLOCK(void __iomem *addr)
void coresight_disable_path(struct list_head *path);
int coresight_enable_path(struct list_head *path);
+struct coresight_device *coresight_get_sink(struct list_head *path);
struct list_head *coresight_build_path(struct coresight_device *csdev);
void coresight_release_path(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 4e326d792100..c02da2edfd80 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -322,6 +322,21 @@ err:
goto out;
}
+struct coresight_device *coresight_get_sink(struct list_head *path)
+{
+ struct coresight_device *csdev;
+
+ if (!path)
+ return NULL;
+
+ csdev = list_last_entry(path, struct coresight_node, link)->csdev;
+ if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
+ csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
+ return NULL;
+
+ return csdev;
+}
+
/**
* _coresight_build_path - recursively build a path from a @csdev to a sink.
* @csdev: The device to start from.
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 01/26] coresight: etm3x: moving etm_readl/writel to header file |
| Message-ID | <qBJse-1YU-15@gated-at.bofh.it> |
| In reply to | #1283374 |
Moving functions etm_readl/writel to file "coresight-etm.h"
so that the main ETM3x driver can be split in more than one
file.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm.h | 29 +++++++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-etm3x.c | 29 ---------------------------
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index b4481eb29304..34f7db881fa7 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -251,4 +251,33 @@ enum etm_addr_type {
ETM_ADDR_TYPE_START,
ETM_ADDR_TYPE_STOP,
};
+
+static inline void etm_writel(struct etm_drvdata *drvdata,
+ u32 val, u32 off)
+{
+ if (drvdata->use_cp14) {
+ if (etm_writel_cp14(off, val)) {
+ dev_err(drvdata->dev,
+ "invalid CP14 access to ETM reg: %#x", off);
+ }
+ } else {
+ writel_relaxed(val, drvdata->base + off);
+ }
+}
+
+static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
+{
+ u32 val;
+
+ if (drvdata->use_cp14) {
+ if (etm_readl_cp14(off, &val)) {
+ dev_err(drvdata->dev,
+ "invalid CP14 access to ETM reg: %#x", off);
+ }
+ } else {
+ val = readl_relaxed(drvdata->base + off);
+ }
+
+ return val;
+}
#endif
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index d630b7ece735..c1dc095c3fb0 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -42,35 +42,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO);
static int etm_count;
static struct etm_drvdata *etmdrvdata[NR_CPUS];
-static inline void etm_writel(struct etm_drvdata *drvdata,
- u32 val, u32 off)
-{
- if (drvdata->use_cp14) {
- if (etm_writel_cp14(off, val)) {
- dev_err(drvdata->dev,
- "invalid CP14 access to ETM reg: %#x", off);
- }
- } else {
- writel_relaxed(val, drvdata->base + off);
- }
-}
-
-static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
-{
- u32 val;
-
- if (drvdata->use_cp14) {
- if (etm_readl_cp14(off, &val)) {
- dev_err(drvdata->dev,
- "invalid CP14 access to ETM reg: %#x", off);
- }
- } else {
- val = readl_relaxed(drvdata->base + off);
- }
-
- return val;
-}
-
/*
* Memory mapped writes to clear os lock are not supported on some processors
* and OS lock must be unlocked before any memory mapped access on such
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 14/26] coresight: etm3x: adding perf_get/set_config() API |
| Message-ID | <qBJse-1YU-27@gated-at.bofh.it> |
| In reply to | #1283374 |
Adding a source operation to build a tracer's configuration from
a perf_event. That way possibly complex parsing of the information
conveyed by the event doesn't have to be carried out every time
the configuration is needed.
Since event configuration can change between concurrent sessions,
the possibility of associating a tracer with a configuration is
also provided. As such Perf can assign session configuration to
tracers as it see fit.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/Kconfig | 1 +
drivers/hwtracing/coresight/coresight-etm3x.c | 70 +++++++++++++++++++++++++++
include/linux/coresight.h | 9 +++-
3 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 6c8921140f02..e252dd1522e5 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -4,6 +4,7 @@
menuconfig CORESIGHT
bool "CoreSight Tracing Support"
select ARM_AMBA
+ select PERF_EVENTS
help
This framework provides a kernel interface for the CoreSight debug
and trace drivers to register themselves with. It's intended to build
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index d0b77be51980..cda28e0211f5 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -31,6 +31,7 @@
#include <linux/seq_file.h>
#include <linux/uaccess.h>
#include <linux/clk.h>
+#include <linux/perf_event.h>
#include <asm/sections.h>
#include "coresight-etm.h"
@@ -315,6 +316,40 @@ void etm_config_trace_mode(struct etm_drvdata *drvdata,
config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
}
+#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN)
+
+static int etm_parse_event_config(struct etm_drvdata *drvdata,
+ struct etm_config *config,
+ struct perf_event *event)
+{
+ u32 mode = 0;
+ u64 event_config = event->attr.config;
+
+ if (event->attr.exclude_kernel)
+ mode = ETM_MODE_EXCL_KERN;
+
+ if (event->attr.exclude_user)
+ mode = ETM_MODE_EXCL_USER;
+
+ /*
+ * By default the tracers are configured to trace the whole address
+ * range. Narrow the field only if requested by user space.
+ */
+ if (mode)
+ etm_config_trace_mode(drvdata, config, mode);
+
+ /*
+ * At this time only cycle accurate and timestamp options are
+ * available.
+ */
+ if (event_config & ~ETM3X_SUPPORTED_OPTIONS)
+ return -EINVAL;
+
+ config->ctrl = event_config;
+
+ return 0;
+}
+
static void etm_enable_hw(void *info)
{
int i;
@@ -428,6 +463,38 @@ static int etm_trace_id(struct coresight_device *csdev)
return etm_get_trace_id(drvdata);
}
+static void *etm_get_config(struct coresight_device *csdev,
+ struct perf_event *event)
+{
+ struct etm_config *config = NULL;
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ config = kzalloc(sizeof(struct etm_config), GFP_KERNEL);
+ if (!config)
+ return config;
+
+ etm_set_default(config);
+
+ if (etm_parse_event_config(drvdata, config, event))
+ return ERR_PTR(-EINVAL);
+
+ return config;
+}
+
+static void etm_put_config(void *config)
+{
+ struct etm_config *cfg = config;
+
+ kfree(cfg);
+}
+
+static void etm_set_config(struct coresight_device *csdev, void *config)
+{
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ drvdata->config = config;
+}
+
static int etm_enable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -569,6 +636,9 @@ static void etm_disable(struct coresight_device *csdev)
static const struct coresight_ops_source etm_source_ops = {
.cpu_id = etm_cpu_id,
.trace_id = etm_trace_id,
+ .get_config = etm_get_config,
+ .put_config = etm_put_config,
+ .set_config = etm_set_config,
.enable = etm_enable,
.disable = etm_disable,
};
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 61dfb8d511ea..da242dfebdbd 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -206,13 +206,20 @@ struct coresight_ops_link {
* @cpu_id: returns the value of the CPU number this component
* is associated to.
* @trace_id: returns the value of the component's trace ID as known
- to the HW.
+ * to the HW.
+ * @get_config: builds the ETM configuration after events' specifics.
+ * @put_config: release memory allocated in @get_config.
+ * @set_config: associate a tracer with a configuration.
* @enable: enables tracing for a source.
* @disable: disables tracing for a source.
*/
struct coresight_ops_source {
int (*cpu_id)(struct coresight_device *csdev);
int (*trace_id)(struct coresight_device *csdev);
+ void *(*get_config)(struct coresight_device *csdev,
+ struct perf_event *event);
+ void (*put_config)(void *config);
+ void (*set_config)(struct coresight_device *csdev, void *config);
int (*enable)(struct coresight_device *csdev, u32 mode);
void (*disable)(struct coresight_device *csdev);
};
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 17/26] coresight: adding operation mode for sink->enable() |
| Message-ID | <qBJsf-1YU-33@gated-at.bofh.it> |
| In reply to | #1283374 |
Adding an operation mode to sink->enable() API in order
to prevent simultaneous access from different callers.
TPIU and TMC won't be supplemented with the AUX area
API immediately and as such ignore the new mode.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 31 +++++++++++++++++++++------
drivers/hwtracing/coresight/coresight-priv.h | 2 +-
drivers/hwtracing/coresight/coresight-tmc.c | 2 +-
drivers/hwtracing/coresight/coresight-tpiu.c | 2 +-
drivers/hwtracing/coresight/coresight.c | 10 ++++-----
include/linux/coresight.h | 2 +-
6 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 09e306361e4f..dc4d707b28aa 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -73,9 +73,9 @@
* @miscdev: specifics to handle "/dev/xyz.etb" entry.
* @spinlock: only one at a time pls.
* @reading: synchronise user space access to etb buffer.
+ * @mode: this ETB is being used.
* @buf: area of memory where ETB buffer content gets sent.
* @buffer_depth: size of @buf.
- * @enable: this ETB is being used.
* @trigger_cntr: amount of words to store after a trigger.
*/
struct etb_drvdata {
@@ -86,9 +86,9 @@ struct etb_drvdata {
struct miscdevice miscdev;
spinlock_t spinlock;
local_t reading;
+ local_t mode;
u8 *buf;
u32 buffer_depth;
- bool enable;
u32 trigger_cntr;
};
@@ -133,18 +133,34 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static int etb_enable(struct coresight_device *csdev)
+static int etb_enable(struct coresight_device *csdev, u32 mode)
{
- struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ u32 val;
unsigned long flags;
+ struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ val = local_cmpxchg(&drvdata->mode,
+ CS_MODE_DISABLED, mode);
+ /*
+ * When accessing from Perf, a HW buffer can be handled
+ * by a single trace entity. In sysFS mode many tracers
+ * can be logging to the same HW buffer.
+ */
+ if (val == CS_MODE_PERF)
+ return -EBUSY;
+
+ /* Nothing to do, the tracer is already enabled. */
+ if (val == CS_MODE_SYSFS)
+ goto out;
spin_lock_irqsave(&drvdata->spinlock, flags);
etb_enable_hw(drvdata);
- drvdata->enable = true;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
+out:
dev_info(drvdata->dev, "ETB enabled\n");
return 0;
+
}
static void etb_disable_hw(struct etb_drvdata *drvdata)
@@ -243,9 +259,10 @@ static void etb_disable(struct coresight_device *csdev)
spin_lock_irqsave(&drvdata->spinlock, flags);
etb_disable_hw(drvdata);
etb_dump_hw(drvdata);
- drvdata->enable = false;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ local_set(&drvdata->mode, CS_MODE_DISABLED);
+
dev_info(drvdata->dev, "ETB disabled\n");
}
@@ -263,7 +280,7 @@ static void etb_dump(struct etb_drvdata *drvdata)
unsigned long flags;
spin_lock_irqsave(&drvdata->spinlock, flags);
- if (drvdata->enable) {
+ if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
etb_disable_hw(drvdata);
etb_dump_hw(drvdata);
etb_enable_hw(drvdata);
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 932f34a84d96..333eddaed339 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -62,7 +62,7 @@ static inline void CS_UNLOCK(void __iomem *addr)
}
void coresight_disable_path(struct list_head *path);
-int coresight_enable_path(struct list_head *path);
+int coresight_enable_path(struct list_head *path, u32 mode);
struct coresight_device *coresight_get_sink(struct list_head *path);
struct list_head *coresight_build_path(struct coresight_device *csdev);
void coresight_release_path(struct list_head *path);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 5e2a71767870..d7e83da7a621 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -265,7 +265,7 @@ static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
return 0;
}
-static int tmc_enable_sink(struct coresight_device *csdev)
+static int tmc_enable_sink(struct coresight_device *csdev, u32 mode)
{
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
index e19b86e61c38..0a09135382f6 100644
--- a/drivers/hwtracing/coresight/coresight-tpiu.c
+++ b/drivers/hwtracing/coresight/coresight-tpiu.c
@@ -70,7 +70,7 @@ static void tpiu_enable_hw(struct tpiu_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static int tpiu_enable(struct coresight_device *csdev)
+static int tpiu_enable(struct coresight_device *csdev, u32 mode)
{
struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index c02da2edfd80..428bcd446eaf 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -121,13 +121,13 @@ static int coresight_find_link_outport(struct coresight_device *csdev,
return 0;
}
-static int coresight_enable_sink(struct coresight_device *csdev)
+static int coresight_enable_sink(struct coresight_device *csdev, u32 mode)
{
int ret;
if (!csdev->enable) {
if (sink_ops(csdev)->enable) {
- ret = sink_ops(csdev)->enable(csdev);
+ ret = sink_ops(csdev)->enable(csdev, mode);
if (ret)
return ret;
}
@@ -283,7 +283,7 @@ void coresight_disable_path(struct list_head *path)
}
}
-int coresight_enable_path(struct list_head *path)
+int coresight_enable_path(struct list_head *path, u32 mode)
{
int ret = 0;
@@ -296,7 +296,7 @@ int coresight_enable_path(struct list_head *path)
switch (csdev->type) {
case CORESIGHT_DEV_TYPE_SINK:
case CORESIGHT_DEV_TYPE_LINKSINK:
- ret = coresight_enable_sink(csdev);
+ ret = coresight_enable_sink(csdev, mode);
if (ret)
goto err;
break;
@@ -454,7 +454,7 @@ int coresight_enable(struct coresight_device *csdev)
goto out;
}
- ret = coresight_enable_path(path);
+ ret = coresight_enable_path(path, CS_MODE_SYSFS);
if (ret)
goto err_path;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index da242dfebdbd..2b94994d2c02 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -185,7 +185,7 @@ struct coresight_device {
* @disable: disables the sink.
*/
struct coresight_ops_sink {
- int (*enable)(struct coresight_device *csdev);
+ int (*enable)(struct coresight_device *csdev, u32 mode);
void (*disable)(struct coresight_device *csdev);
};
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 06/26] coresight: associating path with session rather than tracer |
| Message-ID | <qBJsf-1YU-35@gated-at.bofh.it> |
| In reply to | #1283374 |
When using the Coresight framework from the sysFS interface a
tracer is always handling a single session and as such, a path
can be associated with a tracer. But when supporting multiple
session per tracer there is no guarantee that sessions will always
have the same path from source to sink.
This patch is removing the automatic association between path and
tracers. The building of a path and enablement of the components
in the path are decoupled, allowing for the association of a path
with a session rather than a tracer.
To keep backward functionality with the current sysFS access methods
a per-cpu place holder is used to keep a handle on the path built when
tracers are enabled. Lastly APIs to build paths and enable tracers are
made public so that other subsystem can interact with the Coresight
framework.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-priv.h | 5 +
drivers/hwtracing/coresight/coresight.c | 300 ++++++++++++++++++---------
include/linux/coresight.h | 2 -
3 files changed, 208 insertions(+), 99 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 62fcd98cc7cf..7b193a34d709 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -52,6 +52,11 @@ static inline void CS_UNLOCK(void __iomem *addr)
} while (0);
}
+void coresight_disable_path(struct list_head *path);
+int coresight_enable_path(struct list_head *path);
+struct list_head *coresight_build_path(struct coresight_device *csdev);
+void coresight_release_path(struct list_head *path);
+
#ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
extern int etm_readl_cp14(u32 off, unsigned int *val);
extern int etm_writel_cp14(u32 off, u32 val);
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 93738dfbf631..74beba461aa2 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -29,6 +29,22 @@
static DEFINE_MUTEX(coresight_mutex);
+/**
+ * struct coresight_node - elements of a path, from source to sink
+ * @csdev: Address of an element.
+ * @link: hook to the list.
+ */
+struct coresight_node {
+ struct coresight_device *csdev;
+ struct list_head link;
+};
+
+/*
+ * When operating Coresight drivers from the sysFS interface, only a single
+ * path can exist from a tracer (associated to a CPU) to a sink.
+ */
+static DEFINE_PER_CPU(struct list_head *, sysfs_path);
+
static int coresight_id_match(struct device *dev, void *data)
{
int trace_id, i_trace_id;
@@ -68,15 +84,12 @@ static int coresight_source_is_unique(struct coresight_device *csdev)
csdev, coresight_id_match);
}
-static int coresight_find_link_inport(struct coresight_device *csdev)
+static int coresight_find_link_inport(struct coresight_device *csdev,
+ struct coresight_device *parent)
{
int i;
- struct coresight_device *parent;
struct coresight_connection *conn;
- parent = container_of(csdev->path_link.next,
- struct coresight_device, path_link);
-
for (i = 0; i < parent->nr_outport; i++) {
conn = &parent->conns[i];
if (conn->child_dev == csdev)
@@ -89,15 +102,12 @@ static int coresight_find_link_inport(struct coresight_device *csdev)
return 0;
}
-static int coresight_find_link_outport(struct coresight_device *csdev)
+static int coresight_find_link_outport(struct coresight_device *csdev,
+ struct coresight_device *child)
{
int i;
- struct coresight_device *child;
struct coresight_connection *conn;
- child = container_of(csdev->path_link.prev,
- struct coresight_device, path_link);
-
for (i = 0; i < csdev->nr_outport; i++) {
conn = &csdev->conns[i];
if (conn->child_dev == child)
@@ -138,14 +148,19 @@ static void coresight_disable_sink(struct coresight_device *csdev)
}
}
-static int coresight_enable_link(struct coresight_device *csdev)
+static int coresight_enable_link(struct coresight_device *csdev,
+ struct coresight_device *parent,
+ struct coresight_device *child)
{
int ret;
int link_subtype;
int refport, inport, outport;
- inport = coresight_find_link_inport(csdev);
- outport = coresight_find_link_outport(csdev);
+ if (!parent || !child)
+ return -EINVAL;
+
+ inport = coresight_find_link_inport(csdev, parent);
+ outport = coresight_find_link_outport(csdev, child);
link_subtype = csdev->subtype.link_subtype;
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG)
@@ -168,14 +183,19 @@ static int coresight_enable_link(struct coresight_device *csdev)
return 0;
}
-static void coresight_disable_link(struct coresight_device *csdev)
+static void coresight_disable_link(struct coresight_device *csdev,
+ struct coresight_device *parent,
+ struct coresight_device *child)
{
int i, nr_conns;
int link_subtype;
int refport, inport, outport;
- inport = coresight_find_link_inport(csdev);
- outport = coresight_find_link_outport(csdev);
+ if (!parent || !child)
+ return;
+
+ inport = coresight_find_link_inport(csdev, parent);
+ outport = coresight_find_link_outport(csdev, child);
link_subtype = csdev->subtype.link_subtype;
if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) {
@@ -235,109 +255,167 @@ static void coresight_disable_source(struct coresight_device *csdev)
}
}
-static int coresight_enable_path(struct list_head *path)
+void coresight_disable_path(struct list_head *path)
{
- int ret = 0;
- struct coresight_device *cd;
-
- /*
- * At this point we have a full @path, from source to sink. The
- * sink is the first entry and the source the last one. Go through
- * all the components and enable them one by one.
- */
- list_for_each_entry(cd, path, path_link) {
- if (cd == list_first_entry(path, struct coresight_device,
- path_link)) {
- ret = coresight_enable_sink(cd);
- } else if (list_is_last(&cd->path_link, path)) {
- /*
- * Don't enable the source just yet - this needs to
- * happen at the very end when all links and sink
- * along the path have been configured properly.
- */
- ;
- } else {
- ret = coresight_enable_link(cd);
+ struct coresight_node *nd;
+ struct coresight_device *csdev, *parent, *child;
+
+ list_for_each_entry(nd, path, link) {
+ csdev = nd->csdev;
+
+ switch (csdev->type) {
+ case CORESIGHT_DEV_TYPE_SINK:
+ case CORESIGHT_DEV_TYPE_LINKSINK:
+ coresight_disable_sink(csdev);
+ break;
+ case CORESIGHT_DEV_TYPE_SOURCE:
+ /* sources are disabled from either sysFS or Perf */
+ break;
+ case CORESIGHT_DEV_TYPE_LINK:
+ parent = list_prev_entry(nd, link)->csdev;
+ child = list_next_entry(nd, link)->csdev;
+ coresight_disable_link(csdev, parent, child);
+ break;
+ default:
+ break;
}
- if (ret)
- goto err;
}
+}
- return 0;
-err:
- list_for_each_entry_continue_reverse(cd, path, path_link) {
- if (cd == list_first_entry(path, struct coresight_device,
- path_link)) {
- coresight_disable_sink(cd);
- } else if (list_is_last(&cd->path_link, path)) {
- ;
- } else {
- coresight_disable_link(cd);
+int coresight_enable_path(struct list_head *path)
+{
+
+ int ret = 0;
+ struct coresight_node *nd;
+ struct coresight_device *csdev, *parent, *child;
+
+ list_for_each_entry_reverse(nd, path, link) {
+ csdev = nd->csdev;
+
+ switch (csdev->type) {
+ case CORESIGHT_DEV_TYPE_SINK:
+ case CORESIGHT_DEV_TYPE_LINKSINK:
+ ret = coresight_enable_sink(csdev);
+ if (ret)
+ goto err;
+ break;
+ case CORESIGHT_DEV_TYPE_SOURCE:
+ /* sources are enabled from either sysFS or Perf */
+ break;
+ case CORESIGHT_DEV_TYPE_LINK:
+ parent = list_prev_entry(nd, link)->csdev;
+ child = list_next_entry(nd, link)->csdev;
+ ret = coresight_enable_link(csdev, parent, child);
+ if (ret)
+ goto err;
+ break;
+ default:
+ goto err;
}
}
+out:
return ret;
+err:
+ coresight_disable_path(path);
+ goto out;
}
-static int coresight_disable_path(struct list_head *path)
+/**
+ * _coresight_build_path - recursively build a path from a @csdev to a sink.
+ * @csdev: The device to start from.
+ * @path: The list to add devices to.
+ *
+ * The tree of Coresight device is traversed until an activated sink is
+ * found. From there the sink is added to the list along with all the
+ * devices that led to that point - the end result is a list from source
+ * to sink. In that list the source is the first device and the sink the
+ * last one.
+ */
+static int _coresight_build_path(struct coresight_device *csdev,
+ struct list_head *path)
{
- struct coresight_device *cd;
-
- list_for_each_entry_reverse(cd, path, path_link) {
- if (cd == list_first_entry(path, struct coresight_device,
- path_link)) {
- coresight_disable_sink(cd);
- } else if (list_is_last(&cd->path_link, path)) {
- /*
- * The source has already been stopped, no need
- * to do it again here.
- */
- ;
- } else {
- coresight_disable_link(cd);
+ int i;
+ bool found = false;
+ struct coresight_node *node;
+ struct coresight_connection *conn;
+
+ /* An activated sink has been found. Enqueue the element */
+ if ((csdev->type == CORESIGHT_DEV_TYPE_SINK ||
+ csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) && csdev->activated)
+ goto out;
+
+ /* Not a sink - recursively explore each port found on this element */
+ for (i = 0; i < csdev->nr_outport; i++) {
+ conn = &csdev->conns[i];
+ if (_coresight_build_path(conn->child_dev, path) == 0) {
+ found = true;
+ break;
}
}
+ if (!found)
+ return -ENODEV;
+
+out:
+ /*
+ * A path from this element to a sink has been found. The elements
+ * leading to the sink are already enqueued, all that is left to do
+ * is add a node for this element.
+ */
+ node = kzalloc(sizeof(struct coresight_node), GFP_KERNEL);
+ if (!node)
+ return -ENOMEM;
+
+ node->csdev = csdev;
+ list_add(&node->link, path);
+
return 0;
}
-static int coresight_build_paths(struct coresight_device *csdev,
- struct list_head *path,
- bool enable)
+struct list_head *coresight_build_path(struct coresight_device *csdev)
{
- int i, ret = -EINVAL;
- struct coresight_connection *conn;
+ struct list_head *path;
- list_add(&csdev->path_link, path);
+ path = kzalloc(sizeof(struct list_head), GFP_KERNEL);
+ if (!path)
+ return NULL;
- if ((csdev->type == CORESIGHT_DEV_TYPE_SINK ||
- csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) &&
- csdev->activated) {
- if (enable)
- ret = coresight_enable_path(path);
- else
- ret = coresight_disable_path(path);
- } else {
- for (i = 0; i < csdev->nr_outport; i++) {
- conn = &csdev->conns[i];
- if (coresight_build_paths(conn->child_dev,
- path, enable) == 0)
- ret = 0;
- }
+ INIT_LIST_HEAD(path);
+
+ if (_coresight_build_path(csdev, path)) {
+ kfree(path);
+ path = NULL;
}
- if (list_first_entry(path, struct coresight_device, path_link) != csdev)
- dev_err(&csdev->dev, "wrong device in %s\n", __func__);
+ return path;
+}
- list_del(&csdev->path_link);
+/**
+ * coresight_release_path - release a previously built path.
+ * @path: the path to release.
+ *
+ * Go through all the elements of a path and 1) removed it from the list and
+ * 2) free the memory allocated for each node.
+ */
+void coresight_release_path(struct list_head *path)
+{
+ struct coresight_node *nd, *next;
- return ret;
+ list_for_each_entry_safe(nd, next, path, link) {
+ list_del(&nd->link);
+ kfree(nd);
+ }
+
+ kfree(path);
+ path = NULL;
}
int coresight_enable(struct coresight_device *csdev)
{
int ret = 0;
- LIST_HEAD(path);
+ int cpu;
+ struct list_head *path;
mutex_lock(&coresight_mutex);
if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE) {
@@ -348,22 +426,47 @@ int coresight_enable(struct coresight_device *csdev)
if (csdev->enable)
goto out;
- if (coresight_build_paths(csdev, &path, true)) {
- dev_err(&csdev->dev, "building path(s) failed\n");
+ path = coresight_build_path(csdev);
+ if (!path) {
+ pr_err("building path(s) failed\n");
goto out;
}
- if (coresight_enable_source(csdev))
- dev_err(&csdev->dev, "source enable failed\n");
+ ret = coresight_enable_path(path);
+ if (ret)
+ goto err_path;
+
+ ret = coresight_enable_source(csdev);
+ if (ret)
+ goto err_source;
+
+ /*
+ * When working from sysFS it is important to keep track
+ * of the paths that were created so that they can be
+ * undone in 'coresight_disable()'. Since there can only
+ * be a single session per tracer (when working from sysFS)
+ * a per-cpu variable will do just fine.
+ */
+ cpu = source_ops(csdev)->cpu_id(csdev);
+ per_cpu(sysfs_path, cpu) = path;
+
out:
mutex_unlock(&coresight_mutex);
return ret;
+
+err_source:
+ coresight_disable_path(path);
+
+err_path:
+ coresight_release_path(path);
+ goto out;
}
EXPORT_SYMBOL_GPL(coresight_enable);
void coresight_disable(struct coresight_device *csdev)
{
- LIST_HEAD(path);
+ int cpu;
+ struct list_head *path;
mutex_lock(&coresight_mutex);
if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE) {
@@ -373,9 +476,12 @@ void coresight_disable(struct coresight_device *csdev)
if (!csdev->enable)
goto out;
+ cpu = source_ops(csdev)->cpu_id(csdev);
+ path = per_cpu(sysfs_path, cpu);
coresight_disable_source(csdev);
- if (coresight_build_paths(csdev, &path, false))
- dev_err(&csdev->dev, "releasing path(s) failed\n");
+ coresight_disable_path(path);
+ coresight_release_path(path);
+ per_cpu(sysfs_path, cpu) = NULL;
out:
mutex_unlock(&coresight_mutex);
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index bf62b265bf52..851ecb22397e 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -152,7 +152,6 @@ struct coresight_connection {
by @coresight_ops.
* @dev: The device entity associated to this component.
* @refcnt: keep track of what is in use.
- * @path_link: link of current component into the path being enabled.
* @orphan: true if the component has connections that haven't been linked.
* @enable: 'true' if component is currently part of an active path.
* @activated: 'true' only if a _sink_ has been activated. A sink can be
@@ -168,7 +167,6 @@ struct coresight_device {
const struct coresight_ops *ops;
struct device dev;
atomic_t *refcnt;
- struct list_head path_link;
bool orphan;
bool enable; /* true only if configured as part of a path */
bool activated; /* true only if a sink is part of a path */
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-03 22:20 +0100 |
| Subject | [PATCH V6 13/26] coresight: etm3x: implementing user/kernel mode tracing |
| Message-ID | <qBJsf-1YU-39@gated-at.bofh.it> |
| In reply to | #1283374 |
Adding new mode to limit tracing to kernel or user space.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm.h | 7 ++-
.../hwtracing/coresight/coresight-etm3x-sysfs.c | 4 ++
drivers/hwtracing/coresight/coresight-etm3x.c | 63 ++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-priv.h | 3 ++
4 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index f01862fc98dd..e72815073b63 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -110,7 +110,10 @@
#define ETM_MODE_STALL BIT(2)
#define ETM_MODE_TIMESTAMP BIT(3)
#define ETM_MODE_CTXID BIT(4)
-#define ETM_MODE_ALL 0x1f
+#define ETM_MODE_ALL (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \
+ ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \
+ ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \
+ ETM_MODE_EXCL_USER)
#define ETM_SQR_MASK 0x3
#define ETM_TRACEID_MASK 0x3f
@@ -296,5 +299,7 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
extern const struct attribute_group *coresight_etm_groups[];
int etm_get_trace_id(struct etm_drvdata *drvdata);
void etm_set_default(struct etm_config *config);
+void etm_config_trace_mode(struct etm_drvdata *drvdata,
+ struct etm_config *config, u32 mode);
struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
#endif
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index 6da50d94ec6f..f7318f04118d 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -176,6 +176,10 @@ static ssize_t mode_store(struct device *dev,
config->ctrl |= ETMCR_CTXID_SIZE;
else
config->ctrl &= ~ETMCR_CTXID_SIZE;
+
+ if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
+ etm_config_trace_mode(drvdata, config, config->mode);
+
spin_unlock(&drvdata->spinlock);
return size;
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index 14927da0f6ba..d0b77be51980 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -252,6 +252,69 @@ void etm_set_default(struct etm_config *config)
config->ctxid_mask = 0x0;
}
+void etm_config_trace_mode(struct etm_drvdata *drvdata,
+ struct etm_config *config,
+ u32 mode)
+{
+ u32 flags;
+
+ mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
+
+ /* excluding kernel AND user space doesn't make sense */
+ if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
+ return;
+
+ /* nothing to do if neither flags are set */
+ if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
+ return;
+
+ flags = (1 << 0 | /* instruction execute */
+ 3 << 3 | /* ARM instruction */
+ 0 << 5 | /* No data value comparison */
+ 0 << 7 | /* No exact mach */
+ 0 << 8); /* Ignore context ID */
+
+ /* No need to worry about single address comparators. */
+ config->enable_ctrl2 = 0x0;
+
+ /* Bit 0 is address range comparator 1 */
+ config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
+
+ /*
+ * On ETMv3.5:
+ * ETMACTRn[13,11] == Non-secure state comparison control
+ * ETMACTRn[12,10] == Secure state comparison control
+ *
+ * b00 == Match in all modes in this state
+ * b01 == Do not match in any more in this state
+ * b10 == Match in all modes excepts user mode in this state
+ * b11 == Match only in user mode in this state
+ */
+
+ /* Tracing in secure mode is not supported at this time */
+ flags |= (0 << 12 | 1 << 10);
+
+ if (mode & ETM_MODE_EXCL_USER) {
+ /* exclude user, match all modes except user mode */
+ flags |= (1 << 13 | 0 << 11);
+ } else {
+ /* exclude kernel, match only in user mode */
+ flags |= (1 << 13 | 1 << 11);
+ }
+
+ /*
+ * The ETMEEVR register is already set to "hard wire A". As such
+ * all there is to do is setup an address comparator that spans
+ * the entire address range and configure the state and mode bits.
+ */
+ config->addr_val[0] = (u32) 0x0;
+ config->addr_val[1] = (u32) ~0x0;
+ config->addr_acctype[0] = flags;
+ config->addr_acctype[1] = flags;
+ config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
+ config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
+}
+
static void etm_enable_hw(void *info)
{
int i;
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index ed116b303e87..932f34a84d96 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -34,6 +34,9 @@
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
+#define ETM_MODE_EXCL_KERN BIT(30)
+#define ETM_MODE_EXCL_USER BIT(31)
+
enum cs_mode {
CS_MODE_DISABLED,
CS_MODE_SYSFS,
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-08 21:30 +0100 |
| Message-ID | <qDx3A-728-3@gated-at.bofh.it> |
| In reply to | #1283374 |
On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> This patchset aims to integrate configuration and control of
> the Coresight tracers with the perf sub-system.
>
> The goal is to use PMUs to represent tracers and the auxiliary
> buffer enhancement to collect processor traces. As such a lot
> of work is done to move the current Coresight sysFS oriented
> configuration and control commands to perf's AUX API.
>
> For the time being the work concentrates on ETMv3 and ETB1.0
> sink buffer. Work on ETMv4 and other type of sink buffers
> will follow once a foundation has been established.
>
> Best regards,
> Mathieu
>
> Changes since V5:
> * Addressed Arnaldo's comment about using a struct perf_evlist rather
> than a struct perf_session.
> * Addressed kbuild test robot's anomaly report [1].
> * Moved perf_aux_output_{begin|end} to etm_event_{start|stop} in
> accordance with [2].
>
> [1]. https://lkml.org/lkml/2015/11/30/46
> [2]. http://thread.gmane.org/gmane.linux.kernel/2099328/focus=2099343
>
> Changes since V4:
> * Reworked the way event configuration information is kept, fixing
> a few corner cases when doing per CPU tracing.
> * Rebased on 4.4-rc1.
> * Added 'Cc' to specific perf related patches in the hope of suscitating
> interest from reviewers, i.e perf maintainers.
>
> Changes since V3:
> * Rebased to GKH's char-misc-next tree (e2d8680741ed).
>
> Changes since V2:
> * Rebased to v4.3.
> * Used the -M option to "git format-patch".
> * Decoupled tracers and path - both are now completely independent.
> * Moved path enablement/release to Perf's add/del functions.
> * Moved PM runtime operations to the coresight core rather than
> individual drivers.
> * Enhanced mutual exclusion scheme between perf and sysFS.
> * Removed architecture specific define in perf cmd line tool.
> * Got rid of unused fields in structure 'cs_buffers'.
> * Enhanced changelog for patch 16/26.
>
> Changes since V1:
> * Fixed typos in typographical error in documentation.
> * Moved to a multi session support scheme.
> * Split static and dynamic tracer configuration.
> * Fixed configuration for user and kernel space tracing.
> * Using WARN_ON_ONCE() rather than WARN_ON().
> * Implemented strategy to prevent tracers from being used simultaneously.
> * Changed sink_ops::unset_buffer() to sink_ops::reset_buffer().
> * Moves ETM's sysFS interface from driver core to dedicated file.
> * Removed spinlock in "etm_cpu_id()".
> * Aggregated PMU driver pieces in a single patch.
> * Added user space changes and rebased everything to v4.3-rc5.
>
> Mathieu Poirier (26):
> coresight: etm3x: moving etm_readl/writel to header file
> coresight: etm3x: moving sysFS entries to dedicated file
> coresight: etm3x: unlocking tracers in default arch init
> coresight: etm3x: splitting struct etm_drvdata
> coresight: etm3x: implementing 'cpu_id()' API
> coresight: associating path with session rather than tracer
> coresight: moving PM runtime operations to core framework
> coresight: etm3x: adding operation mode for etm_enable()
> coresight: add API to get sink from path
> coresight: etm3x: set progbit to stop trace collection
> coresight: etm3x: changing default trace configuration
> coresight: etm3x: consolidating initial config
> coresight: etm3x: implementing user/kernel mode tracing
> coresight: etm3x: adding perf_get/set_config() API
> coresight: etm3x: implementing perf_enable/disable() API
> coresight: etb10: moving to local atomic operations
> coresight: adding operation mode for sink->enable()
> coresight: etb10: implementing AUX space API
> coresight: updating documentation to reflect integration with perf
> perf: changing pmu::setup_aux() parameter to include event
> coresight: etm-perf: new PMU driver for ETM tracers
> coresight: introducing a global trace ID function
> perf tools: making function set_max_cpu_num() non static
> perf tools: adding perf_evlist to *info_priv_size()
> perf tools: making coresight PMU listable
> perf tools: adding coresight etm PMU record capabilities
>
> Documentation/trace/coresight.txt | 138 +-
> MAINTAINERS | 4 +
> arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +-
> arch/x86/kernel/cpu/perf_event_intel_pt.c | 5 +-
> drivers/hwtracing/coresight/Kconfig | 1 +
> drivers/hwtracing/coresight/Makefile | 4 +-
> drivers/hwtracing/coresight/coresight-etb10.c | 277 +++-
> drivers/hwtracing/coresight/coresight-etm-perf.c | 447 +++++
> drivers/hwtracing/coresight/coresight-etm-perf.h | 32 +
> drivers/hwtracing/coresight/coresight-etm.h | 143 +-
> .../hwtracing/coresight/coresight-etm3x-sysfs.c | 1442 ++++++++++++++++
> drivers/hwtracing/coresight/coresight-etm3x.c | 1754 +++++---------------
> drivers/hwtracing/coresight/coresight-etm4x.c | 8 +-
> drivers/hwtracing/coresight/coresight-funnel.c | 2 -
> drivers/hwtracing/coresight/coresight-priv.h | 15 +
> .../coresight/coresight-replicator-qcom.c | 4 -
> drivers/hwtracing/coresight/coresight-replicator.c | 2 -
> drivers/hwtracing/coresight/coresight-tmc.c | 7 +-
> drivers/hwtracing/coresight/coresight-tpiu.c | 4 +-
> drivers/hwtracing/coresight/coresight.c | 330 ++--
> include/linux/coresight-pmu.h | 39 +
> include/linux/coresight.h | 40 +-
> include/linux/perf_event.h | 2 +-
> kernel/events/ring_buffer.c | 2 +-
> tools/perf/arch/arm/util/Build | 2 +
> tools/perf/arch/arm/util/auxtrace.c | 48 +
> tools/perf/arch/arm/util/cs_etm.c | 466 ++++++
> tools/perf/arch/arm/util/cs_etm.h | 44 +
> tools/perf/arch/arm/util/pmu.c | 34 +
> tools/perf/arch/x86/util/intel-bts.c | 4 +-
> tools/perf/arch/x86/util/intel-pt.c | 4 +-
> tools/perf/config/Makefile | 17 +-
> tools/perf/util/auxtrace.c | 8 +-
> tools/perf/util/auxtrace.h | 7 +-
> tools/perf/util/cpumap.c | 2 +-
> tools/perf/util/cpumap.h | 1 +
> 36 files changed, 3753 insertions(+), 1590 deletions(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-etm-perf.c
> create mode 100644 drivers/hwtracing/coresight/coresight-etm-perf.h
> create mode 100644 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> create mode 100644 include/linux/coresight-pmu.h
> create mode 100644 tools/perf/arch/arm/util/auxtrace.c
> create mode 100644 tools/perf/arch/arm/util/cs_etm.c
> create mode 100644 tools/perf/arch/arm/util/cs_etm.h
> create mode 100644 tools/perf/arch/arm/util/pmu.c
>
> --
> 2.1.4
>
Arnaldo, Peter and Ingo,
I would like to queue this work for 4.5 but need your help with
reviewing patches 20 [1], 23 [2], 24 [3], 25 [4] and 26 [5].
A "reviewed-by" would be greatly appreciated.
Many thanks,
Mathieu
[1]. https://lkml.org/lkml/2015/12/3/682
[2]. https://lkml.org/lkml/2015/12/3/688
[3]. https://lkml.org/lkml/2015/12/3/683
[4]. https://lkml.org/lkml/2015/12/3/686
[5]. https://lkml.org/lkml/2015/12/3/684
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Arnaldo Carvalho de Melo <acme@kernel.org> |
|---|---|
| Date | 2015-12-08 21:40 +0100 |
| Message-ID | <qDxdg-75c-13@gated-at.bofh.it> |
| In reply to | #1286823 |
Em Tue, Dec 08, 2015 at 01:29:00PM -0700, Mathieu Poirier escreveu: > On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poirier@linaro.org> wrote: > > Arnaldo, Peter and Ingo, > > I would like to queue this work for 4.5 but need your help with > reviewing patches 20 [1], 23 [2], 24 [3], 25 [4] and 26 [5]. > > A "reviewed-by" would be greatly appreciated. I looked briefly at it and saw perf_session, IIRc, being passed to more functions, which I think can be done otherwise, as, again IIRC, all you need is available via perf_evlist, will look again. - Arnaldo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-10 22:30 +0100 |
| Message-ID | <qEgWK-3aC-5@gated-at.bofh.it> |
| In reply to | #1286835 |
On 8 December 2015 at 13:34, Arnaldo Carvalho de Melo <acme@kernel.org> wrote: > Em Tue, Dec 08, 2015 at 01:29:00PM -0700, Mathieu Poirier escreveu: >> On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poirier@linaro.org> wrote: >> >> Arnaldo, Peter and Ingo, >> >> I would like to queue this work for 4.5 but need your help with >> reviewing patches 20 [1], 23 [2], 24 [3], 25 [4] and 26 [5]. >> >> A "reviewed-by" would be greatly appreciated. > > I looked briefly at it and saw perf_session, IIRc, being passed to more > functions, which I think can be done otherwise, as, again IIRC, all you > need is available via perf_evlist, will look again. I just had a double take here and the only remnant of a "struct perf_session" I can see is in 26 [1], but that is following the upstream API [2]. I can send a fix for that but it would be outside the scope of this patch set. Thanks, Mathieu [1]. https://lkml.org/lkml/2015/12/3/684 [2]. http://lxr.free-electrons.com/source/tools/perf/util/auxtrace.h#L293 > > - Arnaldo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2015-12-08 21:30 +0100 |
| Message-ID | <qDx3A-728-5@gated-at.bofh.it> |
| In reply to | #1283374 |
On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> This patchset aims to integrate configuration and control of
> the Coresight tracers with the perf sub-system.
>
> The goal is to use PMUs to represent tracers and the auxiliary
> buffer enhancement to collect processor traces. As such a lot
> of work is done to move the current Coresight sysFS oriented
> configuration and control commands to perf's AUX API.
>
> For the time being the work concentrates on ETMv3 and ETB1.0
> sink buffer. Work on ETMv4 and other type of sink buffers
> will follow once a foundation has been established.
>
> Best regards,
> Mathieu
>
> Changes since V5:
> * Addressed Arnaldo's comment about using a struct perf_evlist rather
> than a struct perf_session.
> * Addressed kbuild test robot's anomaly report [1].
> * Moved perf_aux_output_{begin|end} to etm_event_{start|stop} in
> accordance with [2].
>
> [1]. https://lkml.org/lkml/2015/11/30/46
> [2]. http://thread.gmane.org/gmane.linux.kernel/2099328/focus=2099343
>
> Changes since V4:
> * Reworked the way event configuration information is kept, fixing
> a few corner cases when doing per CPU tracing.
> * Rebased on 4.4-rc1.
> * Added 'Cc' to specific perf related patches in the hope of suscitating
> interest from reviewers, i.e perf maintainers.
>
> Changes since V3:
> * Rebased to GKH's char-misc-next tree (e2d8680741ed).
>
> Changes since V2:
> * Rebased to v4.3.
> * Used the -M option to "git format-patch".
> * Decoupled tracers and path - both are now completely independent.
> * Moved path enablement/release to Perf's add/del functions.
> * Moved PM runtime operations to the coresight core rather than
> individual drivers.
> * Enhanced mutual exclusion scheme between perf and sysFS.
> * Removed architecture specific define in perf cmd line tool.
> * Got rid of unused fields in structure 'cs_buffers'.
> * Enhanced changelog for patch 16/26.
>
> Changes since V1:
> * Fixed typos in typographical error in documentation.
> * Moved to a multi session support scheme.
> * Split static and dynamic tracer configuration.
> * Fixed configuration for user and kernel space tracing.
> * Using WARN_ON_ONCE() rather than WARN_ON().
> * Implemented strategy to prevent tracers from being used simultaneously.
> * Changed sink_ops::unset_buffer() to sink_ops::reset_buffer().
> * Moves ETM's sysFS interface from driver core to dedicated file.
> * Removed spinlock in "etm_cpu_id()".
> * Aggregated PMU driver pieces in a single patch.
> * Added user space changes and rebased everything to v4.3-rc5.
>
> Mathieu Poirier (26):
> coresight: etm3x: moving etm_readl/writel to header file
> coresight: etm3x: moving sysFS entries to dedicated file
> coresight: etm3x: unlocking tracers in default arch init
> coresight: etm3x: splitting struct etm_drvdata
> coresight: etm3x: implementing 'cpu_id()' API
> coresight: associating path with session rather than tracer
> coresight: moving PM runtime operations to core framework
> coresight: etm3x: adding operation mode for etm_enable()
> coresight: add API to get sink from path
> coresight: etm3x: set progbit to stop trace collection
> coresight: etm3x: changing default trace configuration
> coresight: etm3x: consolidating initial config
> coresight: etm3x: implementing user/kernel mode tracing
> coresight: etm3x: adding perf_get/set_config() API
> coresight: etm3x: implementing perf_enable/disable() API
> coresight: etb10: moving to local atomic operations
> coresight: adding operation mode for sink->enable()
> coresight: etb10: implementing AUX space API
> coresight: updating documentation to reflect integration with perf
> perf: changing pmu::setup_aux() parameter to include event
> coresight: etm-perf: new PMU driver for ETM tracers
> coresight: introducing a global trace ID function
> perf tools: making function set_max_cpu_num() non static
> perf tools: adding perf_evlist to *info_priv_size()
> perf tools: making coresight PMU listable
> perf tools: adding coresight etm PMU record capabilities
>
> Documentation/trace/coresight.txt | 138 +-
> MAINTAINERS | 4 +
> arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +-
> arch/x86/kernel/cpu/perf_event_intel_pt.c | 5 +-
> drivers/hwtracing/coresight/Kconfig | 1 +
> drivers/hwtracing/coresight/Makefile | 4 +-
> drivers/hwtracing/coresight/coresight-etb10.c | 277 +++-
> drivers/hwtracing/coresight/coresight-etm-perf.c | 447 +++++
> drivers/hwtracing/coresight/coresight-etm-perf.h | 32 +
> drivers/hwtracing/coresight/coresight-etm.h | 143 +-
> .../hwtracing/coresight/coresight-etm3x-sysfs.c | 1442 ++++++++++++++++
> drivers/hwtracing/coresight/coresight-etm3x.c | 1754 +++++---------------
> drivers/hwtracing/coresight/coresight-etm4x.c | 8 +-
> drivers/hwtracing/coresight/coresight-funnel.c | 2 -
> drivers/hwtracing/coresight/coresight-priv.h | 15 +
> .../coresight/coresight-replicator-qcom.c | 4 -
> drivers/hwtracing/coresight/coresight-replicator.c | 2 -
> drivers/hwtracing/coresight/coresight-tmc.c | 7 +-
> drivers/hwtracing/coresight/coresight-tpiu.c | 4 +-
> drivers/hwtracing/coresight/coresight.c | 330 ++--
> include/linux/coresight-pmu.h | 39 +
> include/linux/coresight.h | 40 +-
> include/linux/perf_event.h | 2 +-
> kernel/events/ring_buffer.c | 2 +-
> tools/perf/arch/arm/util/Build | 2 +
> tools/perf/arch/arm/util/auxtrace.c | 48 +
> tools/perf/arch/arm/util/cs_etm.c | 466 ++++++
> tools/perf/arch/arm/util/cs_etm.h | 44 +
> tools/perf/arch/arm/util/pmu.c | 34 +
> tools/perf/arch/x86/util/intel-bts.c | 4 +-
> tools/perf/arch/x86/util/intel-pt.c | 4 +-
> tools/perf/config/Makefile | 17 +-
> tools/perf/util/auxtrace.c | 8 +-
> tools/perf/util/auxtrace.h | 7 +-
> tools/perf/util/cpumap.c | 2 +-
> tools/perf/util/cpumap.h | 1 +
> 36 files changed, 3753 insertions(+), 1590 deletions(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-etm-perf.c
> create mode 100644 drivers/hwtracing/coresight/coresight-etm-perf.h
> create mode 100644 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> create mode 100644 include/linux/coresight-pmu.h
> create mode 100644 tools/perf/arch/arm/util/auxtrace.c
> create mode 100644 tools/perf/arch/arm/util/cs_etm.c
> create mode 100644 tools/perf/arch/arm/util/cs_etm.h
> create mode 100644 tools/perf/arch/arm/util/pmu.c
>
> --
> 2.1.4
>
Arnaldo, Peter and Ingo,
I would like to queue this work for 4.5 but need your help with
reviewing patches 20 [1], 23 [2], 24 [3], 25 [4] and 26 [5].
A "reviewed-by" would be greatly appreciated.
Many thanks,
Mathieu
[1]. https://lkml.org/lkml/2015/12/3/682
[2]. https://lkml.org/lkml/2015/12/3/688
[3]. https://lkml.org/lkml/2015/12/3/683
[4]. https://lkml.org/lkml/2015/12/3/686
[5]. https://lkml.org/lkml/2015/12/3/684
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web