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Re: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode

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On Mon, Sep 18, 2017 at 10:44:54AM +0100, Robin Murphy wrote:
> On 18/09/17 05:22, Huacai Chen wrote:
> > In non-coherent DMA mode, kernel uses cache flushing operations to
> > maintain I/O coherency, so the dmapool objects should be aligned to
> > ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least
> > on MIPS:
> > 
> > 	Step 1, dma_map_single
> > 	Step 2, cache_invalidate (no writeback)
> > 	Step 3, dma_from_device
> > 	Step 4, dma_unmap_single
> 
> This is a massive red warning flag for the whole series, because DMA
> pools don't work like that. At best, this will do nothing, and at worst
> it is papering over egregious bugs elsewhere. Streaming mappings of
> coherent allocations means completely broken code.

Oh, I hadn't even seen that part.  Yes, dma coherent (and pool)
allocations must never be used for streaming mappings.  I wish we'd
have some debug infrastructure to warn on such uses.

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[PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode Huacai Chen <chenhc@lemote.com> - 2017-09-18 06:30 +0200
  Re: [PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in  non-coherent DMA mode Christoph Hellwig <hch@infradead.org> - 2017-09-18 07:30 +0200
    Re: [PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode "陈华才" <chenhc@lemote.com> - 2017-09-18 09:00 +0200
  Re: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent  DMA mode Robin Murphy <robin.murphy@arm.com> - 2017-09-18 11:50 +0200
    Re: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in  non-coherent DMA mode Christoph Hellwig <hch@infradead.org> - 2017-09-18 18:00 +0200
      Re: [V5, 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode "陈华才" <chenhc@lemote.com> - 2017-09-19 04:30 +0200
  Re: [PATCH V5 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in  non-coherent DMA mode Christoph Hellwig <hch@infradead.org> - 2017-09-18 17:50 +0200

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