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Groups > linux.kernel > #1734259
| From | Christoph Hellwig <hch@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode |
| Date | 2017-09-18 18:00 +0200 |
| Message-ID | <ur6CK-8bR-15@gated-at.bofh.it> (permalink) |
| References | <uqVR0-Xl-1@gated-at.bofh.it> <uqWN4-1xX-5@gated-at.bofh.it> <uqYlP-2Ut-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Mon, Sep 18, 2017 at 03:03:30PM +0800, 陈华才 wrote: > I don't think dma_get_cache_alignment is the "absolute minimum alignment" in all cases. At least on MIPS/Loongson, if we use I/O coherent mode (Cached DMA mode), align block queue to 4Bytes is enough. If we align block queue to dma_get_cache_alignment in I/O coherent mode, there are peformance lost because we cannot use zero-copy in most cases (user buffers are usually not aligned). If you systems is I/O coherent it should report 1 ARCH_DMA_MINALIGN / dma_get_cache_alignment(). Note that many drivers only support 512 byte aligned mappings for block I/O and they've done pretty fine so far.
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[PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN in non-coherent DMA mode Huacai Chen <chenhc@lemote.com> - 2017-09-18 06:30 +0200
Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN in non-coherent DMA mode Christoph Hellwig <hch@infradead.org> - 2017-09-18 07:30 +0200
Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode "陈华才" <chenhc@lemote.com> - 2017-09-18 09:10 +0200
Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN innon-coherent DMA mode Christoph Hellwig <hch@infradead.org> - 2017-09-18 18:00 +0200
Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN in non-coherent DMA mode kbuild test robot <lkp@intel.com> - 2017-09-18 07:30 +0200
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