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Re: [PATCH 05/13] irqchip: add initial support for ompic

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On 03/09/17 23:12, Stafford Horne wrote:
> On Fri, Sep 01, 2017 at 06:25:01PM +0100, Marc Zyngier wrote:
>> On 01/09/17 02:24, Stafford Horne wrote:
>>> On Thu, Aug 31, 2017 at 10:28:01AM +0100, Marc Zyngier wrote:
>>>> On 30/08/17 22:58, Stafford Horne wrote:
>>>>> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

[...]

>>>>> +	unsigned int dst_cpu;
>>>>> +	unsigned int src_cpu = smp_processor_id();
>>>>> +
>>>>> +	for_each_cpu(dst_cpu, mask) {
>>>>> +		set_bit(irq, &ipi_data[dst_cpu].ops);
>>>>> +
>>>>> +		ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
>>>>> +			       OMPIC_IPI_CTRL_IRQ_GEN |
>>>>> +			       OMPIC_IPI_CTRL_DST(dst_cpu) |
>>>>> +			       OMPIC_IPI_DATA(1));
>>>>
>>>> What guarantees that the action of set_bit can be observed by the target
>>>> CPU? set-bit gives you atomicity, but no barrier.
>>>
>>> The bit will not be read by target CPUs until after the ompic_writereg()
>>> which will trigger the target CPU interrupt to be raised.  OpenRISC stores
>>> are ordered.
>>
>> Are they really ordered irrespective of the memory type (one is
>> cacheable RAM, the other is a device...)?
>>
>> And assuming they are (which I find a bit odd), that doesn't necessarily
>> guarantee that the interrupt will only be delivered once the effect of
>> set_bit can be seen on the target CPU...
> 
> OpenRISC might be a bit odd here, but I think this is correct.  On OpenRISC
> the atomic instructions also imply a pipeline flush for stores and loads
> (l.swa/l.lwa).  This is highlighted in the architecture spec section 7.3 [0].

OK, fair enough. This is quite unusual (and I'm prepared to bet that
this will be relaxed in future evolutions of the architecture), but
that's indeed the gospel.

Please add a comment between set_bit and writereg so that we know we've
been through this discussion already.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

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[PATCH 00/13] OpenRISC SMP Support Stafford Horne <shorne@gmail.com> - 2017-08-31 00:00 +0200
  [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for  simulators Mark Rutland <mark.rutland@arm.com> - 2017-08-31 12:50 +0200
      Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for  simulators Stafford Horne <shorne@gmail.com> - 2017-08-31 15:10 +0200
  [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save  regs on exception Geert Uytterhoeven <geert@linux-m68k.org> - 2017-09-01 10:10 +0200
      Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save  regs on exception Stafford Horne <shorne@gmail.com> - 2017-09-01 10:30 +0200
    Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save  regs on exception Geert Uytterhoeven <geert@linux-m68k.org> - 2017-09-01 10:10 +0200
  [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [PATCH 05/13] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-08-31 11:30 +0200
      Re: [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-01 03:30 +0200
        Re: [PATCH 05/13] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-09-01 19:30 +0200
          Re: [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-04 00:20 +0200
            Re: [PATCH 05/13] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-09-04 09:40 +0200
    Re: [PATCH 05/13] irqchip: add initial support for ompic Mark Rutland <mark.rutland@arm.com> - 2017-08-31 13:10 +0200
      Re: [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-01 16:00 +0200
  [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Peter Zijlstra <peterz@infradead.org> - 2017-08-31 09:50 +0200
      Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne <shorne@gmail.com> - 2017-08-31 11:10 +0200
  [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Geert Uytterhoeven <geert@linux-m68k.org> - 2017-09-01 10:10 +0200
      Re: [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne <shorne@gmail.com> - 2017-09-01 10:30 +0200
  [PATCH 06/13] openrisc: initial SMP support Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200

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