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[PATCH 04/13] openrisc: use qspinlocks and qrwlocks

From Stafford Horne <shorne@gmail.com>
Newsgroups linux.kernel
Subject [PATCH 04/13] openrisc: use qspinlocks and qrwlocks
Date 2017-08-31 00:10 +0200
Message-ID <ukjlp-5CT-53@gated-at.bofh.it> (permalink)
References <ukjbI-5jw-5@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/Kconfig                      |  2 ++
 arch/openrisc/include/asm/Kbuild           |  4 ++++
 arch/openrisc/include/asm/spinlock.h       | 12 +++++++++++-
 arch/openrisc/include/asm/spinlock_types.h |  7 +++++++
 4 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 8ddfc92ab813..214c837ce597 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -28,6 +28,8 @@ config OPENRISC
 	select OR1K_PIC
 	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
 	select NO_BOOTMEM
+	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_RWLOCKS
 
 config CPU_BIG_ENDIAN
 	def_bool y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5bea416a7792..5f066780d870 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -28,6 +28,10 @@ generic-y += module.h
 generic-y += pci.h
 generic-y += percpu.h
 generic-y += preempt.h
+generic-y += qspinlock_types.h
+generic-y += qspinlock.h
+generic-y += qrwlock_types.h
+generic-y += qrwlock.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += string.h
diff --git a/arch/openrisc/include/asm/spinlock.h b/arch/openrisc/include/asm/spinlock.h
index fd00a3a24123..9b761e0e22c3 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -19,6 +19,16 @@
 #ifndef __ASM_OPENRISC_SPINLOCK_H
 #define __ASM_OPENRISC_SPINLOCK_H
 
-#error "or32 doesn't do SMP yet"
+#include <asm/qspinlock.h>
+
+#include <asm/qrwlock.h>
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock)	cpu_relax()
+#define arch_read_relax(lock)	cpu_relax()
+#define arch_write_relax(lock)	cpu_relax()
+
 
 #endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..7c6fb1208c88
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
+#define _ASM_OPENRISC_SPINLOCK_TYPES_H
+
+#include <asm/qspinlock_types.h>
+#include <asm/qrwlock_types.h>
+
+#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
-- 
2.13.5

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Thread

[PATCH 00/13] OpenRISC SMP Support Stafford Horne <shorne@gmail.com> - 2017-08-31 00:00 +0200
  [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for  simulators Mark Rutland <mark.rutland@arm.com> - 2017-08-31 12:50 +0200
      Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for  simulators Stafford Horne <shorne@gmail.com> - 2017-08-31 15:10 +0200
  [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save  regs on exception Geert Uytterhoeven <geert@linux-m68k.org> - 2017-09-01 10:10 +0200
      Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save  regs on exception Stafford Horne <shorne@gmail.com> - 2017-09-01 10:30 +0200
    Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save  regs on exception Geert Uytterhoeven <geert@linux-m68k.org> - 2017-09-01 10:10 +0200
  [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [PATCH 05/13] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-08-31 11:30 +0200
      Re: [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-01 03:30 +0200
        Re: [PATCH 05/13] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-09-01 19:30 +0200
          Re: [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-04 00:20 +0200
            Re: [PATCH 05/13] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-09-04 09:40 +0200
    Re: [PATCH 05/13] irqchip: add initial support for ompic Mark Rutland <mark.rutland@arm.com> - 2017-08-31 13:10 +0200
      Re: [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-01 16:00 +0200
  [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Peter Zijlstra <peterz@infradead.org> - 2017-08-31 09:50 +0200
      Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne <shorne@gmail.com> - 2017-08-31 11:10 +0200
  [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
  [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200
    Re: [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Geert Uytterhoeven <geert@linux-m68k.org> - 2017-09-01 10:10 +0200
      Re: [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne <shorne@gmail.com> - 2017-09-01 10:30 +0200
  [PATCH 06/13] openrisc: initial SMP support Stafford Horne <shorne@gmail.com> - 2017-08-31 00:10 +0200

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