Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1713923

[PATCH v5 10/16] mtd: nand: qcom: add command elements in BAM transaction

Show all headers | View raw

All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.

Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---

* Changes from v4: None

* BUILD DEPENDENCY:

  This PATCH has build dependency over following BAM command descriptor
  patch posted in DMA engine mailing list

  http://www.spinics.net/lists/dmaengine/msg13665.html

 drivers/mtd/nand/qcom_nandc.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 7977a70..b0a4734 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/delay.h>
+#include <linux/dma/qcom_bam_dma.h>
 
 /* NANDc reg offsets */
 #define	NAND_FLASH_CMD			0x00
@@ -199,6 +200,7 @@
  */
 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
 
+#define QPIC_PER_CW_CMD_ELEMENTS	32
 #define QPIC_PER_CW_CMD_SGL		32
 #define QPIC_PER_CW_DATA_SGL		8
 
@@ -221,8 +223,13 @@
 /*
  * This data type corresponds to the BAM transaction which will be used for all
  * NAND transfers.
+ * @bam_ce - the array of BAM command elements
  * @cmd_sgl - sgl for NAND BAM command pipe
  * @data_sgl - sgl for NAND BAM consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ *		   for current sgl. It will be used for size calculation
+ *		   for current sgl
  * @cmd_sgl_pos - current index in command sgl.
  * @cmd_sgl_start - start index in command sgl.
  * @tx_sgl_pos - current index in data sgl for tx.
@@ -231,8 +238,11 @@
  * @rx_sgl_start - start index in data sgl for rx.
  */
 struct bam_transaction {
+	struct bam_cmd_element *bam_ce;
 	struct scatterlist *cmd_sgl;
 	struct scatterlist *data_sgl;
+	u32 bam_ce_pos;
+	u32 bam_ce_start;
 	u32 cmd_sgl_pos;
 	u32 cmd_sgl_start;
 	u32 tx_sgl_pos;
@@ -462,7 +472,8 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
 
 	bam_txn_size =
 		sizeof(*bam_txn) + num_cw *
-		((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+		((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+		(sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
 		(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
 
 	bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
@@ -472,6 +483,10 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
 	bam_txn = bam_txn_buf;
 	bam_txn_buf += sizeof(*bam_txn);
 
+	bam_txn->bam_ce = bam_txn_buf;
+	bam_txn_buf +=
+		sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
 	bam_txn->cmd_sgl = bam_txn_buf;
 	bam_txn_buf +=
 		sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
@@ -489,6 +504,8 @@ static void clear_bam_transaction(struct qcom_nand_controller *nandc)
 	if (!nandc->props->is_bam)
 		return;
 
+	bam_txn->bam_ce_pos = 0;
+	bam_txn->bam_ce_start = 0;
 	bam_txn->cmd_sgl_pos = 0;
 	bam_txn->cmd_sgl_start = 0;
 	bam_txn->tx_sgl_pos = 0;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread

Thread

[PATCH v5 00/16] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 01/16] mtd: nand: qcom: DMA mapping support for register read buffer Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 06/16] mtd: nand: qcom: erased codeword detection configuration Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 08/16] mtd: nand: qcom: QPIC data descriptors handling Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 16/16] mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 07/16] mtd: nand: qcom: enable BAM or ADM mode Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 14/16] dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
    Re: [PATCH v5 14/16] dt-bindings: qcom_nandc: IPQ8074 QPIC NAND  documentation Rob Herring <robh@kernel.org> - 2017-08-22 04:30 +0200
  [PATCH v5 05/16] mtd: nand: qcom: support for read location registers Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 12/16] dt-bindings: qcom_nandc: fix the ipq806x device tree example Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 11/16] mtd: nand: qcom: support for command descriptor formation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
    Re: [PATCH v5 11/16] mtd: nand: qcom: support for command descriptor  formation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-19 11:50 +0200
      Re: [PATCH v5 11/16] mtd: nand: qcom: support for command  descriptor formation Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-08-19 22:40 +0200
  [PATCH v5 10/16] mtd: nand: qcom: add command elements in BAM transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
    Re: [PATCH v5 10/16] mtd: nand: qcom: add command elements in BAM  transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-08-19 11:40 +0200
  [PATCH v5 03/16] mtd: nand: qcom: add BAM DMA descriptor handling Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 13/16] dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 04/16] mtd: nand: qcom: support for passing flags in DMA helper functions Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  [PATCH v5 15/16] mtd: nand: qcom: support for IPQ4019 QPIC NAND controller Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  [PATCH v5 09/16] mtd: nand: qcom: support for different DEV_CMD register offsets Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  [PATCH v5 02/16] mtd: nand: qcom: allocate BAM transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  Re: [PATCH v5 00/16] Add QCOM QPIC NAND support Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-08-21 22:20 +0200
    Re: [PATCH v5 00/16] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-08-22 08:40 +0200

csiph-web