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Groups > linux.kernel > #1713911

[PATCH v5 07/16] mtd: nand: qcom: enable BAM or ADM mode

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1. DM_EN is only required for EBI2 NAND controller which uses ADM
2. BAM mode will be disabled after power on reset which needs to
   be enabled before starting any BAM transfers.

Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---

* Changes from v4: None

 drivers/mtd/nand/qcom_nandc.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 81cfce7..fd77d59 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -163,6 +163,9 @@
 #define NAND_DEV_CMD_VLD_VAL		(READ_START_VLD | WRITE_START_VLD | \
 					 ERASE_START_VLD | SEQ_READ_START_VLD)
 
+/* NAND_CTRL bits */
+#define	BAM_MODE_EN			BIT(0)
+
 /*
  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
  * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -1042,7 +1045,8 @@ static int read_id(struct qcom_nand_host *host, int column)
 	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
 	nandc_set_reg(nandc, NAND_ADDR0, column);
 	nandc_set_reg(nandc, NAND_ADDR1, 0);
-	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
+		      nandc->props->is_bam ? 0 : DM_EN);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
 	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
@@ -2414,12 +2418,19 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
 /* one time setup of a few nand controller registers */
 static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
 {
+	u32 nand_ctrl;
+
 	/* kill onenand */
 	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
 	nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
 
-	/* enable ADM DMA */
-	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+	/* enable ADM or BAM DMA */
+	if (nandc->props->is_bam) {
+		nand_ctrl = nandc_read(nandc, NAND_CTRL);
+		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+	} else {
+		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+	}
 
 	/* save the original values of these registers */
 	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

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[PATCH v5 00/16] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 01/16] mtd: nand: qcom: DMA mapping support for register read buffer Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 06/16] mtd: nand: qcom: erased codeword detection configuration Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 08/16] mtd: nand: qcom: QPIC data descriptors handling Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 16/16] mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 07/16] mtd: nand: qcom: enable BAM or ADM mode Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 14/16] dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
    Re: [PATCH v5 14/16] dt-bindings: qcom_nandc: IPQ8074 QPIC NAND  documentation Rob Herring <robh@kernel.org> - 2017-08-22 04:30 +0200
  [PATCH v5 05/16] mtd: nand: qcom: support for read location registers Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 12/16] dt-bindings: qcom_nandc: fix the ipq806x device tree example Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 11/16] mtd: nand: qcom: support for command descriptor formation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
    Re: [PATCH v5 11/16] mtd: nand: qcom: support for command descriptor  formation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-19 11:50 +0200
      Re: [PATCH v5 11/16] mtd: nand: qcom: support for command  descriptor formation Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-08-19 22:40 +0200
  [PATCH v5 10/16] mtd: nand: qcom: add command elements in BAM transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
    Re: [PATCH v5 10/16] mtd: nand: qcom: add command elements in BAM  transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-08-19 11:40 +0200
  [PATCH v5 03/16] mtd: nand: qcom: add BAM DMA descriptor handling Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 13/16] dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:10 +0200
  [PATCH v5 04/16] mtd: nand: qcom: support for passing flags in DMA helper functions Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  [PATCH v5 15/16] mtd: nand: qcom: support for IPQ4019 QPIC NAND controller Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  [PATCH v5 09/16] mtd: nand: qcom: support for different DEV_CMD register offsets Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  [PATCH v5 02/16] mtd: nand: qcom: allocate BAM transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-08-17 14:20 +0200
  Re: [PATCH v5 00/16] Add QCOM QPIC NAND support Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-08-21 22:20 +0200
    Re: [PATCH v5 00/16] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-08-22 08:40 +0200

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