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[PATCH 4/4] MIPS: microMIPS: Fix decoding of swsp16 instruction

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When the immediate encoded in the instruction is accessed, it is sign
extended due to being a signed value being assigned to a signed integer.
The ISA specifies that this operation is an unsigned operation.
The sign extension leads us to incorrectly decode:

801e9c8e:       cbf1            sw      ra,68(sp)

As having an immediate of 1073741809.

Since the instruction format does not specify signed/unsigned, and this
is currently the only location to use this instuction format, change it
to an unsigned immediate.

Fixes: bb9bc4689b9c ("MIPS: Calculate microMIPS ra properly when unwinding the stack")
Suggested-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>

---

 arch/mips/include/uapi/asm/inst.h | 2 +-
 arch/mips/kernel/process.c        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 77429d1622b3..711d9b8465b8 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -964,7 +964,7 @@ struct mm16_r3_format {		/* Load from global pointer format */
 struct mm16_r5_format {		/* Load/store from stack pointer format */
 	__BITFIELD_FIELD(unsigned int opcode : 6,
 	__BITFIELD_FIELD(unsigned int rt : 5,
-	__BITFIELD_FIELD(signed int simmediate : 5,
+	__BITFIELD_FIELD(unsigned int imm : 5,
 	__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 	;))))
 };
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 6ba5b775579c..67182baaf719 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -212,7 +212,7 @@ static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
 			if (ip->mm16_r5_format.rt != 31)
 				return 0;
 
-			*poff = ip->mm16_r5_format.simmediate;
+			*poff = ip->mm16_r5_format.imm;
 			*poff = (*poff << 2) / sizeof(ulong);
 			return 1;
 
-- 
2.7.4

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Thread

[PATCH 0/4] MIPS: Further microMIPS stack unwinding fixes Matt Redfearn <matt.redfearn@imgtec.com> - 2017-02-28 16:40 +0100
  Re: [PATCH 1/4] MIPS: Handle non word sized instructions when  examining frame "Maciej W. Rozycki" <macro@imgtec.com> - 2017-02-28 22:00 +0100
    Re: [PATCH 1/4] MIPS: Handle non word sized instructions when  examining frame Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 15:10 +0100
  Re: [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp  instruction "Maciej W. Rozycki" <macro@imgtec.com> - 2017-03-01 03:00 +0100
    Re: [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 16:50 +0100
  [PATCH 4/4] MIPS: microMIPS: Fix decoding of swsp16 instruction Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100
  [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100
  [PATCH 1/4] MIPS: Handle non word sized instructions when examining frame Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100
  [PATCH 3/4] MIPS: Stacktrace: Fix __usermode() of uninitialised regs Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100

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