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[PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction

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Commit 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
added handling of microMIPS instructions to manipulate the stack
pointer. Unfortunately the decoding of the addiusp instruction was
incorrect, and performed a left shift by 2 bits to the raw immediate,
rather than decoding the immediate and then performing the shift, as
documented in the ISA.

This led to incomplete stack traces, due to incorrect frame sizes being
calculated. For example the instruction:
801faee0 <do_sys_poll>:
801faee0:       4e25            addiu   sp,sp,-952

As decoded by objdump, would be interpreted by the existing code as
having manipulated the stack pointer by +1096.

Fix this by changing the order of decoding the immediate and applying
the left shift.

Fixes: 34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
---

 arch/mips/kernel/process.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 5b1e932ae973..6ba5b775579c 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -386,8 +386,9 @@ static int get_frame_info(struct mips_frame_info *info)
 
 					if (ip->halfword[0] & mm_addiusp_func)
 					{
-						tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2);
-						info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0));
+						tmp = (ip->halfword[0] >> 1) & 0x1ff;
+						tmp = tmp | ((tmp & 0x100) ? 0xfe00 : 0);
+						info->frame_size = -(signed short)(tmp << 2);
 					} else {
 						tmp = (ip->halfword[0] >> 1);
 						info->frame_size = -(signed short)(tmp & 0xf);
-- 
2.7.4

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Thread

[PATCH 0/4] MIPS: Further microMIPS stack unwinding fixes Matt Redfearn <matt.redfearn@imgtec.com> - 2017-02-28 16:40 +0100
  Re: [PATCH 1/4] MIPS: Handle non word sized instructions when  examining frame "Maciej W. Rozycki" <macro@imgtec.com> - 2017-02-28 22:00 +0100
    Re: [PATCH 1/4] MIPS: Handle non word sized instructions when  examining frame Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 15:10 +0100
  Re: [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp  instruction "Maciej W. Rozycki" <macro@imgtec.com> - 2017-03-01 03:00 +0100
    Re: [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 16:50 +0100
  [PATCH 4/4] MIPS: microMIPS: Fix decoding of swsp16 instruction Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100
  [PATCH 2/4] MIPS: microMIPS: Fix decoding of addiusp instruction Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100
  [PATCH 1/4] MIPS: Handle non word sized instructions when examining frame Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100
  [PATCH 3/4] MIPS: Stacktrace: Fix __usermode() of uninitialised regs Matt Redfearn <matt.redfearn@imgtec.com> - 2017-03-01 08:40 +0100

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