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Groups > linux.kernel > #1587470
| From | Jonas Bonn <jonas@southpole.se> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups |
| Date | 2017-02-24 10:50 +0100 |
| Message-ID | <tekFI-6GV-5@gated-at.bofh.it> (permalink) |
| References | <tefPH-3gU-5@gated-at.bofh.it> <tefPJ-3gU-67@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 02/24/2017 05:32 AM, Stafford Horne wrote: > Cleanups to whitespace and add some comments. Reading through the delay > slot logic I noticed some things: > - Delay slot instructions were not indented > - Some comments are not lined up > - Use tabs and spaces consistent with other code > > No functional change No, don't do this. Whitespace cleanups like this make life difficult for people rebasing on your tree, as well as blunting useful tools like git blame. I'm not against the indentation of the delay slot instructions; that seems sane and should be pretty transparent in a merge conflict. The whitespace cleanup and tab-space toggling needs to go, though. These sorts of things are better fixed up when the code lines they apply to are changed for other, functional reasons. I suggest you pull out the delay slot fixups into a separate patch and then just sit on the rest until you've discovered the pain of whitespace cleanup-inflicted merge conflicts and decide to just ditch them altogether. /Jonas > > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > arch/openrisc/kernel/entry.S | 38 ++++++++++++++++++-------------------- > 1 file changed, 18 insertions(+), 20 deletions(-) > > diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S > index ba1a361..daae2a4 100644 > --- a/arch/openrisc/kernel/entry.S > +++ b/arch/openrisc/kernel/entry.S > @@ -228,7 +228,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler) > * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part > */ > #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX > - l.lwz r6,PT_PC(r3) // address of an offending insn > + l.lwz r6,PT_PC(r3) // address of an offending insn > l.lwz r6,0(r6) // instruction that caused pf > > l.srli r6,r6,26 // check opcode for jump insn > @@ -244,49 +244,47 @@ EXCEPTION_ENTRY(_data_page_fault_handler) > l.bf 8f > l.sfeqi r6,0x12 // l.jalr > l.bf 8f > - > - l.nop > + l.nop > > l.j 9f > - l.nop > -8: > + l.nop > > - l.lwz r6,PT_PC(r3) // address of an offending insn > +8: // offending insn is in delay slot > + l.lwz r6,PT_PC(r3) // address of an offending insn > l.addi r6,r6,4 > l.lwz r6,0(r6) // instruction that caused pf > l.srli r6,r6,26 // get opcode > -9: > +9: // offending instruction opcode loaded in r6 > > #else > > - l.mfspr r6,r0,SPR_SR // SR > -// l.lwz r6,PT_SR(r3) // ESR > - l.andi r6,r6,SPR_SR_DSX // check for delay slot exception > - l.sfeqi r6,0x1 // exception happened in delay slot > - l.bnf 7f > - l.lwz r6,PT_PC(r3) // address of an offending insn > + l.mfspr r6,r0,SPR_SR // SR > + l.andi r6,r6,SPR_SR_DSX // check for delay slot exception > + l.sfeqi r6,0x1 // exception happened in delay slot > + l.bnf 7f > + l.lwz r6,PT_PC(r3) // address of an offending insn > > - l.addi r6,r6,4 // offending insn is in delay slot > + l.addi r6,r6,4 // offending insn is in delay slot > 7: > l.lwz r6,0(r6) // instruction that caused pf > l.srli r6,r6,26 // check opcode for write access > #endif > > - l.sfgeui r6,0x33 // check opcode for write access > + l.sfgeui r6,0x33 // check opcode for write access > l.bnf 1f > l.sfleui r6,0x37 > l.bnf 1f > l.ori r6,r0,0x1 // write access > l.j 2f > - l.nop > + l.nop > 1: l.ori r6,r0,0x0 // !write access > 2: > > /* call fault.c handler in or32/mm/fault.c */ > l.jal do_page_fault > - l.nop > + l.nop > l.j _ret_from_exception > - l.nop > + l.nop > > /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ > EXCEPTION_ENTRY(_itlb_miss_page_fault_handler) > @@ -306,9 +304,9 @@ EXCEPTION_ENTRY(_insn_page_fault_handler) > > /* call fault.c handler in or32/mm/fault.c */ > l.jal do_page_fault > - l.nop > + l.nop > l.j _ret_from_exception > - l.nop > + l.nop > > > /* ---[ 0x500: Timer exception ]----------------------------------------- */
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[PATCH v4 00/24] OpenRISC patches for 4.11 Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 23/24] openrisc: Export ioremap symbols used by modules Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 13/24] openrisc: Initial support for the idle state Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Tobias Klauser <tklauser@distanz.ch> - 2017-02-24 16:00 +0100
Re: [PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Stafford Horne <shorne@gmail.com> - 2017-02-24 20:40 +0100
[PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Jonas Bonn <jonas@southpole.se> - 2017-02-24 10:50 +0100
Re: [PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Stafford Horne <shorne@gmail.com> - 2017-02-24 21:00 +0100
[PATCH v4 08/24] openrisc: add cmpxchg and xchg implementations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 20/24] openrisc: entry: Fix delay slot detection Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 20/24] openrisc: entry: Fix delay slot detection Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:00 +0100
Re: [PATCH v4 20/24] openrisc: entry: Fix delay slot detection Stafford Horne <shorne@gmail.com> - 2017-02-24 21:20 +0100
[PATCH v4 09/24] openrisc: add optimized atomic operations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 04/24] openrisc: head: use THREAD_SIZE instead of magic constant Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 07/24] openrisc: add atomic bitops Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 07/24] openrisc: add atomic bitops Peter Zijlstra <peterz@infradead.org> - 2017-02-24 12:00 +0100
Re: [PATCH v4 07/24] openrisc: add atomic bitops Stafford Horne <shorne@gmail.com> - 2017-02-24 20:30 +0100
[PATCH v4 11/24] openrisc: remove unnecessary stddef.h include Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 01/24] openrisc: use SPARSE_IRQ Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 21/24] openrisc: head: Move init strings to rodata section Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 21/24] openrisc: head: Move init strings to rodata section Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:00 +0100
Re: [PATCH v4 21/24] openrisc: head: Move init strings to rodata section Stafford Horne <shorne@gmail.com> - 2017-02-24 21:20 +0100
[PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:00 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> - 2017-02-24 12:10 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Jonas Bonn <jonas@southpole.se> - 2017-02-24 13:50 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> - 2017-02-24 15:00 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stafford Horne <shorne@gmail.com> - 2017-02-24 20:30 +0100
[PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:10 +0100
Re: [PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Stafford Horne <shorne@gmail.com> - 2017-02-24 20:40 +0100
[PATCH v4 17/24] MAINTAINERS: Add the openrisc official repository Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 12/24] openrisc: Fix the bitmask for the unit present register Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Jonas Bonn <jonas@southpole.se> - 2017-02-24 10:50 +0100
Re: [PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Stafford Horne <shorne@gmail.com> - 2017-02-24 21:00 +0100
[PATCH v4 10/24] openrisc: add futex_atomic_* implementations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 03/24] openrisc: tlb miss handler optimizations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Jonas Bonn <jonas@southpole.se> - 2017-02-24 10:50 +0100
Re: [PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Stafford Horne <shorne@gmail.com> - 2017-02-24 21:40 +0100
[PATCH v4 15/24] openrisc: Add optimized memcpy routine Stafford Horne <shorne@gmail.com> - 2017-02-24 05:50 +0100
[PATCH v4 16/24] openrisc: Add .gitignore Stafford Horne <shorne@gmail.com> - 2017-02-24 05:50 +0100
[PATCH v4 14/24] openrisc: Add optimized memset Stafford Horne <shorne@gmail.com> - 2017-02-24 05:50 +0100
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