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Groups > linux.kernel > #1587477
| From | Jonas Bonn <jonas@southpole.se> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function |
| Date | 2017-02-24 11:00 +0100 |
| Message-ID | <tekPn-6Kt-5@gated-at.bofh.it> (permalink) |
| References | <tefPH-3gU-5@gated-at.bofh.it> <tefPI-3gU-55@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 02/24/2017 05:32 AM, Stafford Horne wrote: > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> > > This brings it inline with the other setup oprations done like the cache > enables _ic_enable and _dc_enable. Also, this is going to make it > easier to initialize additional cpu's when smp is introduced. This patch confuses me. The TLB flush is moved to a point after MMU's are enabled. The TLB flush should happen before enabling the MMU, shouldn't it? /Jonas > > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> > [shorne@gmail.com: Added commit body] > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > arch/openrisc/kernel/head.S | 38 ++++++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 16 deletions(-) > > diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S > index 63ba2d9..a22f1fc 100644 > --- a/arch/openrisc/kernel/head.S > +++ b/arch/openrisc/kernel/head.S > @@ -522,22 +522,8 @@ enable_dc: > l.nop > > flush_tlb: > - /* > - * I N V A L I D A T E T L B e n t r i e s > - */ > - LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0)) > - LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0)) > - l.addi r7,r0,128 /* Maximum number of sets */ > -1: > - l.mtspr r5,r0,0x0 > - l.mtspr r6,r0,0x0 > - > - l.addi r5,r5,1 > - l.addi r6,r6,1 > - l.sfeq r7,r0 > - l.bnf 1b > - l.addi r7,r7,-1 > - > + l.jal _flush_tlb > + l.nop > > /* The MMU needs to be enabled before or32_early_setup is called */ > > @@ -629,6 +615,26 @@ jump_start_kernel: > l.jr r30 > l.nop > > +_flush_tlb: > + /* > + * I N V A L I D A T E T L B e n t r i e s > + */ > + LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0)) > + LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0)) > + l.addi r7,r0,128 /* Maximum number of sets */ > +1: > + l.mtspr r5,r0,0x0 > + l.mtspr r6,r0,0x0 > + > + l.addi r5,r5,1 > + l.addi r6,r6,1 > + l.sfeq r7,r0 > + l.bnf 1b > + l.addi r7,r7,-1 > + > + l.jr r9 > + l.nop > + > /* ========================================[ cache ]=== */ > > /* aligment here so we don't change memory offsets with
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[PATCH v4 00/24] OpenRISC patches for 4.11 Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 23/24] openrisc: Export ioremap symbols used by modules Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 13/24] openrisc: Initial support for the idle state Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Tobias Klauser <tklauser@distanz.ch> - 2017-02-24 16:00 +0100
Re: [PATCH v4 18/24] scripts/checkstack.pl: Add openrisc support Stafford Horne <shorne@gmail.com> - 2017-02-24 20:40 +0100
[PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Jonas Bonn <jonas@southpole.se> - 2017-02-24 10:50 +0100
Re: [PATCH v4 22/24] arch/openrisc/lib/memcpy.c: use correct OR1200 option Stafford Horne <shorne@gmail.com> - 2017-02-24 21:00 +0100
[PATCH v4 08/24] openrisc: add cmpxchg and xchg implementations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 20/24] openrisc: entry: Fix delay slot detection Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 20/24] openrisc: entry: Fix delay slot detection Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:00 +0100
Re: [PATCH v4 20/24] openrisc: entry: Fix delay slot detection Stafford Horne <shorne@gmail.com> - 2017-02-24 21:20 +0100
[PATCH v4 09/24] openrisc: add optimized atomic operations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 04/24] openrisc: head: use THREAD_SIZE instead of magic constant Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 07/24] openrisc: add atomic bitops Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 07/24] openrisc: add atomic bitops Peter Zijlstra <peterz@infradead.org> - 2017-02-24 12:00 +0100
Re: [PATCH v4 07/24] openrisc: add atomic bitops Stafford Horne <shorne@gmail.com> - 2017-02-24 20:30 +0100
[PATCH v4 11/24] openrisc: remove unnecessary stddef.h include Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 01/24] openrisc: use SPARSE_IRQ Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 21/24] openrisc: head: Move init strings to rodata section Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 21/24] openrisc: head: Move init strings to rodata section Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:00 +0100
Re: [PATCH v4 21/24] openrisc: head: Move init strings to rodata section Stafford Horne <shorne@gmail.com> - 2017-02-24 21:20 +0100
[PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:00 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> - 2017-02-24 12:10 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Jonas Bonn <jonas@southpole.se> - 2017-02-24 13:50 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> - 2017-02-24 15:00 +0100
Re: [PATCH v4 05/24] openrisc: head: refactor out tlb flush into it's own function Stafford Horne <shorne@gmail.com> - 2017-02-24 20:30 +0100
[PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Jonas Bonn <jonas@southpole.se> - 2017-02-24 11:10 +0100
Re: [PATCH v4 24/24] openrisc: head: Init r0 to 0 on start Stafford Horne <shorne@gmail.com> - 2017-02-24 20:40 +0100
[PATCH v4 17/24] MAINTAINERS: Add the openrisc official repository Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 12/24] openrisc: Fix the bitmask for the unit present register Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Jonas Bonn <jonas@southpole.se> - 2017-02-24 10:50 +0100
Re: [PATCH v4 06/24] openrisc: add l.lwa/l.swa emulation Stafford Horne <shorne@gmail.com> - 2017-02-24 21:00 +0100
[PATCH v4 10/24] openrisc: add futex_atomic_* implementations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 03/24] openrisc: tlb miss handler optimizations Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
[PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Stafford Horne <shorne@gmail.com> - 2017-02-24 05:40 +0100
Re: [PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Jonas Bonn <jonas@southpole.se> - 2017-02-24 10:50 +0100
Re: [PATCH v4 19/24] openrisc: entry: Whitespace and comment cleanups Stafford Horne <shorne@gmail.com> - 2017-02-24 21:40 +0100
[PATCH v4 15/24] openrisc: Add optimized memcpy routine Stafford Horne <shorne@gmail.com> - 2017-02-24 05:50 +0100
[PATCH v4 16/24] openrisc: Add .gitignore Stafford Horne <shorne@gmail.com> - 2017-02-24 05:50 +0100
[PATCH v4 14/24] openrisc: Add optimized memset Stafford Horne <shorne@gmail.com> - 2017-02-24 05:50 +0100
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