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Groups > linux.kernel > #1675261
| Path | csiph.com!news.redatomik.org!aioe.org!bofh.it!news.nic.it!robomod |
|---|---|
| From | Zhi Mao <zhi.mao@mediatek.com> |
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2 5/6] pwm: mediatek: add PWM_CLK_DIV_MAX |
| Date | Tue, 27 Jun 2017 05:00:01 +0200 |
| Message-ID | <tWOTn-2Bi-5@gated-at.bofh.it> (permalink) |
| References | <tVp0Z-6lw-7@gated-at.bofh.it> <tVp0Z-6lw-15@gated-at.bofh.it> <tWxSy-8w1-19@gated-at.bofh.it> |
| X-Original-To | m18063 <Claudiu.Beznea@microchip.com> |
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| Sender | robomod@news.nic.it |
| List-ID | <linux-kernel.vger.kernel.org> |
| X-Mailing-List | linux-kernel@vger.kernel.org |
| Approved | robomod@news.nic.it |
| Lines | 46 |
| Organization | linux.* mail to news gateway |
| X-Original-Cc | <john@phrozen.org>, Thierry Reding <thierry.reding@gmail.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Matthias Brugger <matthias.bgg@gmail.com>, <linux-pwm@vger.kernel.org>, <zhenbao.liu@mediatek.com>, <devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>, <sean.wang@mediatek.com>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <yt.shen@mediatek.com>, <yingjoe.chen@mediatek.com>, <linux-arm-kernel@lists.infradead.org> |
| X-Original-Date | Tue, 27 Jun 2017 10:50:15 +0800 |
| X-Original-Message-ID | <1498531815.22478.3.camel@mhfsdcap03> |
| X-Original-References | <1498194505-30930-1-git-send-email-zhi.mao@mediatek.com> <1498194505-30930-6-git-send-email-zhi.mao@mediatek.com> <8eaabcb6-c7b1-efcc-7dae-967a38feb8f1@microchip.com> |
| X-Original-Sender | linux-kernel-owner@vger.kernel.org |
| Xref | csiph.com linux.kernel:1675261 |
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On Mon, 2017-06-26 at 11:43 +0300, m18063 wrote:
>
> On 23.06.2017 08:08, Zhi Mao wrote:
> > Replace "7" with "PWM_CLK_DIV_MAX" in function:mtk_pwm_config()
> > to improve the code readablity.
> >
> > Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
> > ---
> > drivers/pwm/pwm-mediatek.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> > index 554a042..e5f6425 100644
> > --- a/drivers/pwm/pwm-mediatek.c
> > +++ b/drivers/pwm/pwm-mediatek.c
> > @@ -30,6 +30,8 @@
> > #define PWMDWIDTH 0x2c
> > #define PWMTHRES 0x30
> >
> > +#define PWM_CLK_DIV_MAX 7
> > +
> > enum {
> > MTK_CLK_MAIN = 0,
> > MTK_CLK_TOP,
> > @@ -130,8 +132,10 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > clkdiv++;
> > }
> >
> > - if (clkdiv > 7)
> > + if (clkdiv > PWM_CLK_DIV_MAX) {
> You forgot to:
> mtk_pwm_clk_disable(chip, pwm);
Hi Claudiu,
Thanks for your suggestion.
It's a problem, I will modify this in the next release.
Regards,
Zhi
> > + dev_err(chip->dev, "period %d not supported\n", period_ns);
> > return -EINVAL;
> > + }
> >
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
> > mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
> >
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[PATCH v2 5/6] pwm: mediatek: add PWM_CLK_DIV_MAX Zhi Mao <zhi.mao@mediatek.com> - 2017-06-23 07:10 +0200
Re: [PATCH v2 5/6] pwm: mediatek: add PWM_CLK_DIV_MAX m18063 <Claudiu.Beznea@microchip.com> - 2017-06-26 10:50 +0200
Re: [PATCH v2 5/6] pwm: mediatek: add PWM_CLK_DIV_MAX Zhi Mao <zhi.mao@mediatek.com> - 2017-06-27 05:00 +0200
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