Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable

From	Peter De Schrijver <pdeschrijver@nvidia.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
Date	2017-05-04 09:50 +0200
Message-ID	<tDjGq-p9-23@gated-at.bofh.it> (permalink)
References	<tyjH4-ye-21@gated-at.bofh.it> <tyT7Q-5t1-5@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote:
> On 04/20, Peter De Schrijver wrote:
> > PLL SS was only controlled when setting the PLL rate, not when the PLL
> > itself is enabled or disabled. This means that if the PLL rate was set
> > before the PLL is enabled, SS will not be enabled, even when configured.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> 
> Fixes tag? Or this isn't a problem right now, just future fix?
> 

This isn't a problem right now, at least noone complained about it.

Peter.

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Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-05-04 09:50 +0200

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