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Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable

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On 04/20, Peter De Schrijver wrote:
> PLL SS was only controlled when setting the PLL rate, not when the PLL
> itself is enabled or disabled. This means that if the PLL rate was set
> before the PLL is enabled, SS will not be enabled, even when configured.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

Fixes tag? Or this isn't a problem right now, just future fix?

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[PATCH] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-04-20 14:50 +0200
  Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable Stephen Boyd <sboyd@codeaurora.org> - 2017-04-22 04:40 +0200

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