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[PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI

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With atomic modesetting the hardware will be powered off when the
mode_set function is called.  We should configure the hardware in the
commit function (or even the enable function, but switching from commit
to enable is left for a future patch).

Signed-off-by: John Keeping <john@metanate.com>
---
v2:
- also move dw_mipi_dsi_get_lane_bps into the commit function
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 45 ++++++++++++++--------------------
 1 file changed, 19 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index d9aa382bb629..8b83ae50c8f3 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -819,34 +819,8 @@ static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 					struct drm_display_mode *adjusted_mode)
 {
 	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
-	int ret;
 
 	dsi->mode = adjusted_mode;
-
-	ret = dw_mipi_dsi_get_lane_bps(dsi);
-	if (ret < 0)
-		return;
-
-	if (clk_prepare_enable(dsi->pclk)) {
-		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
-		return;
-	}
-
-	dw_mipi_dsi_init(dsi);
-	dw_mipi_dsi_dpi_config(dsi, mode);
-	dw_mipi_dsi_packet_handler_config(dsi);
-	dw_mipi_dsi_video_mode_config(dsi);
-	dw_mipi_dsi_video_packet_config(dsi, mode);
-	dw_mipi_dsi_command_mode_config(dsi);
-	dw_mipi_dsi_line_timer_config(dsi);
-	dw_mipi_dsi_vertical_timing_config(dsi);
-	dw_mipi_dsi_dphy_timing_config(dsi);
-	dw_mipi_dsi_dphy_interface_config(dsi);
-	dw_mipi_dsi_clear_err(dsi);
-	if (drm_panel_prepare(dsi->panel))
-		dev_err(dsi->dev, "failed to prepare panel\n");
-
-	clk_disable_unprepare(dsi->pclk);
 }
 
 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
@@ -880,12 +854,31 @@ static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
 	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 	int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 	u32 val;
+	int ret;
+
+	ret = dw_mipi_dsi_get_lane_bps(dsi);
+	if (ret < 0)
+		return;
 
 	if (clk_prepare_enable(dsi->pclk)) {
 		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 		return;
 	}
 
+	dw_mipi_dsi_init(dsi);
+	dw_mipi_dsi_dpi_config(dsi, dsi->mode);
+	dw_mipi_dsi_packet_handler_config(dsi);
+	dw_mipi_dsi_video_mode_config(dsi);
+	dw_mipi_dsi_video_packet_config(dsi, dsi->mode);
+	dw_mipi_dsi_command_mode_config(dsi);
+	dw_mipi_dsi_line_timer_config(dsi);
+	dw_mipi_dsi_vertical_timing_config(dsi);
+	dw_mipi_dsi_dphy_timing_config(dsi);
+	dw_mipi_dsi_dphy_interface_config(dsi);
+	dw_mipi_dsi_clear_err(dsi);
+	if (drm_panel_prepare(dsi->panel))
+		dev_err(dsi->dev, "failed to prepare panel\n");
+
 	dw_mipi_dsi_phy_init(dsi);
 	dw_mipi_dsi_wait_for_two_frames(dsi);
 
-- 
2.11.0.197.gb556de5.dirty

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Thread

[PATCH v2 00/26] drm/rockchip: MIPI fixes & improvements John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 12/26] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control Chris Zhong <zyw@rock-chips.com> - 2017-01-23 07:20 +0100
  [PATCH v2 05/26] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds  read on tx_buf Chris Zhong <zyw@rock-chips.com> - 2017-01-22 07:50 +0100
  [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure  PHY timing Chris Zhong <zyw@rock-chips.com> - 2017-01-22 04:10 +0100
  [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll  helper Chris Zhong <zyw@rock-chips.com> - 2017-01-23 02:00 +0100
  [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in  error message Chris Zhong <zyw@rock-chips.com> - 2017-01-22 07:50 +0100
  [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook Chris Zhong <zyw@rock-chips.com> - 2017-01-22 07:20 +0100
  [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate Chris Zhong <zyw@rock-chips.com> - 2017-01-22 10:40 +0100
  [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL  until it's configured Chris Zhong <zyw@rock-chips.com> - 2017-01-22 11:20 +0100
  [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset Chris Zhong <zyw@rock-chips.com> - 2017-01-22 10:40 +0100
  [PATCH v2 02/26] drm/rockchip: dw-mipi-dsi: rename commit hook to enable John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure  hardware in mode_set for MIPI Chris Zhong <zyw@rock-chips.com> - 2017-01-22 05:00 +0100

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