Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]


Groups > linux.kernel > #1564177

[PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured

From John Keeping <john@metanate.com>
Newsgroups linux.kernel
Subject [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured
Date 2017-01-21 17:40 +0100
Message-ID <t26RR-6cn-69@gated-at.bofh.it> (permalink)
References <t26RP-6cn-9@gated-at.bofh.it>
Organization linux.* mail to news gateway

Show all headers | View raw


Signed-off-by: John Keeping <john@metanate.com>
---
Unchanged in v2
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index ce1e6f9a2041..cfe7e4ba305c 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -413,12 +413,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 
 	dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 
-	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 	dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 					 LOW_PROGRAM_EN);
 	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 					 HIGH_PROGRAM_EN);
+	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 
 	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 					 BIASEXTR_SEL(BIASEXTR_127_7));
-- 
2.11.0.197.gb556de5.dirty

Back to linux.kernel | Previous | NextPrevious in thread | Next in thread | Find similar | Unroll thread


Thread

[PATCH v2 00/26] drm/rockchip: MIPI fixes & improvements John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 12/26] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 25/26] drm/rockchip: dw-mipi-dsi: add reset control Chris Zhong <zyw@rock-chips.com> - 2017-01-23 07:20 +0100
  [PATCH v2 05/26] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 07/26] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds  read on tx_buf Chris Zhong <zyw@rock-chips.com> - 2017-01-22 07:50 +0100
  [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure  PHY timing Chris Zhong <zyw@rock-chips.com> - 2017-01-22 04:10 +0100
  [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 20/26] drm/rockchip: dw-mipi-dsi: use specific poll  helper Chris Zhong <zyw@rock-chips.com> - 2017-01-23 02:00 +0100
  [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 08/26] drm/rockchip: dw-mipi-dsi: include bad value in  error message Chris Zhong <zyw@rock-chips.com> - 2017-01-22 07:50 +0100
  [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 04/26] drm/rockchip: dw-mipi-dsi: remove mode_set hook Chris Zhong <zyw@rock-chips.com> - 2017-01-22 07:20 +0100
  [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 14/26] drm/rockchip: dw-mipi-dsi: fix escape clock rate Chris Zhong <zyw@rock-chips.com> - 2017-01-22 10:40 +0100
  [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL  until it's configured Chris Zhong <zyw@rock-chips.com> - 2017-01-22 11:20 +0100
  [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 15/26] drm/rockchip: dw-mipi-dsi: ensure PHY is reset Chris Zhong <zyw@rock-chips.com> - 2017-01-22 10:40 +0100
  [PATCH v2 02/26] drm/rockchip: dw-mipi-dsi: rename commit hook to enable John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
  [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping <john@metanate.com> - 2017-01-21 17:40 +0100
    Re: [PATCH v2 01/26] drm/rockchip: dw-mipi-dsi: don't configure  hardware in mode_set for MIPI Chris Zhong <zyw@rock-chips.com> - 2017-01-22 05:00 +0100

csiph-web