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Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins

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On Tue, Sep 27, 2016 at 4:50 PM, Andrew Jeffery <andrew@aj.id.au> wrote:

> The initial Aspeed pinctrl patches implemented a subset of pins for each of the
> g4 and g5 SoCs. This series provides a number of fixes to the initial patches,
> mostly for issues identified in the g5 driver. The fixes account for the first
> half of the series (up to and including "pinctrl: aspeed-g5: Fix pin
> association of SPI1 function") and should be applied for 4.9.

Those are applied for fixes.

> The second half, from "pinctrl: aspeed: Enable capture of off-SCU pinmux
> state", implements some additional functionality in the core engine for the
> Aspeed SoCs and follows up with patches implementing mux configuration tables
> for all remaining pins. Given the significant additions in the last few
> patches, their lateness in the cycle and the light testing they have received
> they are best left for 4.10, but I'm keen to get them out for review.

I'm holding these back until v4.9-rc1 is out.

Yours,
Linus Walleij

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[PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins Andrew Jeffery <andrew@aj.id.au> - 2016-09-27 17:00 +0200
  [PATCH 1/8] pinctrl: aspeed: "Not enabled" is a significant mux state Andrew Jeffery <andrew@aj.id.au> - 2016-09-27 17:00 +0200
    Re: [PATCH 1/8] pinctrl: aspeed: "Not enabled" is a significant mux state Joel Stanley <joel@jms.id.au> - 2016-09-29 03:00 +0200
  [PATCH 2/8] pinctrl: aspeed-g5: Fix names of GPID2 pins Andrew Jeffery <andrew@aj.id.au> - 2016-09-27 17:00 +0200
    Re: [PATCH 2/8] pinctrl: aspeed-g5: Fix names of GPID2 pins Linus Walleij <linus.walleij@linaro.org> - 2016-10-10 10:00 +0200
  [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux state Andrew Jeffery <andrew@aj.id.au> - 2016-09-27 17:00 +0200
    Re: [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux state Joel Stanley <joel@jms.id.au> - 2016-09-29 08:50 +0200
      Re: [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux  state Andrew Jeffery <andrew@aj.id.au> - 2016-09-29 10:00 +0200
  Re: [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins Joel Stanley <joel@jms.id.au> - 2016-09-29 03:00 +0200
  Re: [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all  pins Rob Herring <robh@kernel.org> - 2016-10-03 21:10 +0200
    Re: [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all  pins Andrew Jeffery <andrew@aj.id.au> - 2016-10-04 03:10 +0200
  Re: [PATCH 8/8] pinctrl: aspeed-g5: Add mux configuration for all  pins Rob Herring <robh@kernel.org> - 2016-10-10 03:00 +0200
  Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement  remaining pins Linus Walleij <linus.walleij@linaro.org> - 2016-10-10 10:10 +0200
    Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement  remaining pins Andrew Jeffery <andrew@aj.id.au> - 2016-10-11 01:40 +0200

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