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[PATCH v4 1/9] arm64: cpufeature: treat unknown fields as RES0

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From: Mark Rutland <mark.rutland@arm.com>

Any fields not defined in an arm64_ftr_bits entry are propagated to the
system-wide register value in init_cpu_ftr_reg(), and while we require
that these strictly match for the sanity checks, we don't update them in
update_cpu_ftr_reg().

Generally, the lack of an arm64_ftr_bits entry indicates that the bits
are currently RES0 (as is the case for the upper 32 bits of all
supposedly 32-bit registers).

A better default would be to use zero for the system-wide value of
unallocated bits, making all register checking consistent, and allowing
for subsequent simplifications to the arm64_ftr_bits arrays.

This patch updates init_cpu_ftr_reg() to treat unallocated bits as RES0
for the purpose of the system-wide safe value. These bits will still be
sanity checked with strict match requirements, as is currently the case.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index fdf8f04..ea02201 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -410,23 +410,33 @@ static void __init sort_ftr_regs(void)
 /*
  * Initialise the CPU feature register from Boot CPU values.
  * Also initiliases the strict_mask for the register.
+ * Any bits that are not covered by an arm64_ftr_bits entry are considered
+ * RES0 for the system-wide value, and must strictly match.
  */
 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 {
 	u64 val = 0;
 	u64 strict_mask = ~0x0ULL;
+	u64 valid_mask = 0;
+
 	const struct arm64_ftr_bits *ftrp;
 	struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 
 	BUG_ON(!reg);
 
 	for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
+		u64 ftr_mask = arm64_ftr_mask(ftrp);
 		s64 ftr_new = arm64_ftr_value(ftrp, new);
 
 		val = arm64_ftr_set_value(ftrp, val, ftr_new);
+
+		valid_mask |= ftr_mask;
 		if (!ftrp->strict)
-			strict_mask &= ~arm64_ftr_mask(ftrp);
+			strict_mask &= ~ftr_mask;
 	}
+
+	val &= valid_mask;
+
 	reg->sys_val = val;
 	reg->strict_mask = strict_mask;
 }
-- 
2.7.4

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[PATCH v4 0/9] arm64: Expose CPUID registers via emulation Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
  [PATCH v4 4/9] arm64: cpufeature: Document the rules of safe value for features Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
  [PATCH v4 9/9] arm64: Documentation - Expose CPU feature registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
  [PATCH v4 1/9] arm64: cpufeature: treat unknown fields as RES0 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
  [PATCH v4 3/9] arm64: cpufeature: Cleanup feature bit tables Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
  [PATCH v4 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
    Re: [PATCH v4 7/9] arm64: cpufeature: Track user visible fields Catalin Marinas <catalin.marinas@arm.com> - 2017-01-10 15:30 +0100
      Re: [PATCH v4 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-01-10 15:30 +0100
  [PATCH v4 6/9] arm64: Add helper to decode register from instruction Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-09 18:40 +0100
  Re: [PATCH v4 0/9] arm64: Expose CPUID registers via emulation Will Deacon <will.deacon@arm.com> - 2017-01-10 18:20 +0100

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