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Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages

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Le 14/08/2016 à 16:25, Aneesh Kumar K.V a écrit :
> Christophe Leroy <christophe.leroy@c-s.fr> writes:
>
>> The 8xx has 512k and 8M pages. This patch implements hugepages using
>> those sizes.
>>
>> On the 8xx, the size of pages is in the PGD entry,
>> using PS field (bits 28-29):
>> 00 : Small pages (4k or 16k)
>> 01 : 512k pages
>> 10 : reserved
>> 11 : 8M pages
>>
>> The implementation uses a mix of what is used on BOOKS and BOOKE,
>> as 512k pages are in HUGEPTE tables while for 8M pages we have
>> several PGD entries pointing on a leaf HUGEPTE entry
>>
>> For the time being, we do not support CPU15 ERRATA if HUGETLB is
>> selected
>
> Can you also document here the format for linux page table with different
> huge page size. ?

Euh ... isn't it what I do when explaining the use of the PS field in 
the PGD entry ? That's the thing, that's how the 8xx knows how it is a 
huge page, and that's how Linux will know it is one. On the 8xx, the 
Linux PGD entry (almost) match the L1 MMU entry and the Linux PTE almost 
match the L2 MMU entry (some bits are copied from the PTE to the L1 
entry and then removed from the value writen to the L2 MMU entry)

Christophe

>
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

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[PATCH 0/6] powerpc/8xx: implementation of huge pages Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
  [PATCH 2/6] powerpc: fix usage of _PAGE_RO in hugepage Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
  [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
    Re: [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-14 16:20 +0200
      Re: [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits christophe leroy <christophe.leroy@c-s.fr> - 2016-08-14 21:00 +0200
        Re: [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-15 12:30 +0200
  [PATCH 4/6] powerpc/8xx: Move additional DTLBMiss handlers out of  exception area Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
  [PATCH 5/6] powerpc/8xx: make user addr DTLB miss the short path Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
  [PATCH 3/6] powerpc/8xx: use r3 to scratch CR in ITLBmiss Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
  [PATCH 6/6] powerpc/8xx: implementation of huge pages Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
    Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-14 16:30 +0200
      Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages christophe leroy <christophe.leroy@c-s.fr> - 2016-08-14 19:40 +0200
        Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-15 12:40 +0200
  Re: [PATCH 0/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-14 16:30 +0200
    Re: [PATCH 0/6] powerpc/8xx: implementation of huge pages christophe leroy <christophe.leroy@c-s.fr> - 2016-08-14 19:40 +0200
      Re: [PATCH 0/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-15 12:40 +0200

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