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Groups > linux.kernel > #1462135
| From | "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages |
| Date | 2016-08-14 16:30 +0200 |
| Message-ID | <s64Ai-M3-1@gated-at.bofh.it> (permalink) |
| References | <s5nYl-4bK-5@gated-at.bofh.it> <s5nYm-4bK-17@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Christophe Leroy <christophe.leroy@c-s.fr> writes: > The 8xx has 512k and 8M pages. This patch implements hugepages using > those sizes. > > On the 8xx, the size of pages is in the PGD entry, > using PS field (bits 28-29): > 00 : Small pages (4k or 16k) > 01 : 512k pages > 10 : reserved > 11 : 8M pages > > The implementation uses a mix of what is used on BOOKS and BOOKE, > as 512k pages are in HUGEPTE tables while for 8M pages we have > several PGD entries pointing on a leaf HUGEPTE entry > > For the time being, we do not support CPU15 ERRATA if HUGETLB is > selected Can you also document here the format for linux page table with different huge page size. ? > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
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[PATCH 0/6] powerpc/8xx: implementation of huge pages Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
[PATCH 2/6] powerpc: fix usage of _PAGE_RO in hugepage Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
[PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
Re: [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-14 16:20 +0200
Re: [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits christophe leroy <christophe.leroy@c-s.fr> - 2016-08-14 21:00 +0200
Re: [PATCH 1/6] powerpc: port 64 bits pgtable_cache to 32 bits "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-15 12:30 +0200
[PATCH 4/6] powerpc/8xx: Move additional DTLBMiss handlers out of exception area Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
[PATCH 5/6] powerpc/8xx: make user addr DTLB miss the short path Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
[PATCH 3/6] powerpc/8xx: use r3 to scratch CR in ITLBmiss Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
[PATCH 6/6] powerpc/8xx: implementation of huge pages Christophe Leroy <christophe.leroy@c-s.fr> - 2016-08-12 19:00 +0200
Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-14 16:30 +0200
Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages christophe leroy <christophe.leroy@c-s.fr> - 2016-08-14 19:40 +0200
Re: [PATCH 6/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-15 12:40 +0200
Re: [PATCH 0/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-14 16:30 +0200
Re: [PATCH 0/6] powerpc/8xx: implementation of huge pages christophe leroy <christophe.leroy@c-s.fr> - 2016-08-14 19:40 +0200
Re: [PATCH 0/6] powerpc/8xx: implementation of huge pages "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> - 2016-08-15 12:40 +0200
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