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Groups > linux.kernel > #1399385
| From | Laxman Dewangan <ldewangan@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage |
| Date | 2016-05-11 19:40 +0200 |
| Message-ID | <rxGh4-4oy-9@gated-at.bofh.it> (permalink) |
| References | (2 earlier) <rvP58-6Z1-27@gated-at.bofh.it> <rvQaS-7UW-1@gated-at.bofh.it> <rwvQJ-6Pc-1@gated-at.bofh.it> <rxCGv-Pf-13@gated-at.bofh.it> <rxEoV-2BM-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wednesday 11 May 2016 09:05 PM, Jon Hunter wrote: > On 11/05/16 14:28, Laxman Dewangan wrote: >> On Sunday 08 May 2016 05:43 PM, Jon Hunter wrote: >>> On 06/05/16 16:32, Laxman Dewangan wrote: >>>> On Friday 06 May 2016 08:07 PM, Jon Hunter wrote: >>>>> On 06/05/16 11:45, Laxman Dewangan wrote: >>>>> + >>>>> + /* Last entry */ >>>>> + TEGRA_IO_PAD_MAX, >>>>> Nit should these be TEGRA_IO_PADS_xxx? >>>> Because this was name of single pad and hence I said TEGRA_IO_PAD_XXX. >>> Aren't these used to set the voltage level and power state for the >>> entire group of IOs? Confused :-( >> One IO pad can have multiple IO pins. >> IO Pad control the power state and voltage of all pins belongs to that >> IO pad. > Ugh ... I remember for xusb there was something similar we the Tegra > docs used pad to imply multiple. However, in general pad == pin == ball > or at least should. when we say sddmc3 IO pads, we deal with all signal pins of sdmm3.
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[PATCH V4 0/3] soc/tegra: Add support for IO pads power and voltage control Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
[PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-06 16:40 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 17:50 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-08 14:20 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-11 15:50 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-11 17:40 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-11 19:40 +0200
Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-11 22:00 +0200
[PATCH V4 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
Re: [PATCH V4 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() Jon Hunter <jonathanh@nvidia.com> - 2016-05-06 16:20 +0200
[PATCH V4 1/3] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
Re: [PATCH V4 1/3] soc/tegra: pmc: Use BIT macro for register field definition Jon Hunter <jonathanh@nvidia.com> - 2016-05-06 16:20 +0200
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