Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage

From	Jon Hunter <jonathanh@nvidia.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage
Date	2016-05-11 17:40 +0200
Message-ID	<rxEoV-2BM-7@gated-at.bofh.it> (permalink)
References	(1 earlier) <rvLEe-3qs-3@gated-at.bofh.it> <rvP58-6Z1-27@gated-at.bofh.it> <rvQaS-7UW-1@gated-at.bofh.it> <rwvQJ-6Pc-1@gated-at.bofh.it> <rxCGv-Pf-13@gated-at.bofh.it>
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On 11/05/16 14:28, Laxman Dewangan wrote:
> On Sunday 08 May 2016 05:43 PM, Jon Hunter wrote:
>> On 06/05/16 16:32, Laxman Dewangan wrote:
>>> On Friday 06 May 2016 08:07 PM, Jon Hunter wrote:
>>>> On 06/05/16 11:45, Laxman Dewangan wrote:
>>>> +
>>>> +    /* Last entry */
>>>> +    TEGRA_IO_PAD_MAX,
>>>> Nit should these be TEGRA_IO_PADS_xxx?
>>> Because this was name of single pad and hence I said TEGRA_IO_PAD_XXX.
>> Aren't these used to set the voltage level and power state for the
>> entire group of IOs? Confused :-(
> 
> One IO pad can have multiple IO pins.
> IO Pad control the power state and voltage of all pins belongs to that
> IO pad.

Ugh ... I remember for xusb there was something similar we the Tegra
docs used pad to imply multiple. However, in general pad == pin == ball
or at least should.

> Now what should we say PADS or PAD here? TEGRA_IO_PAD_UART or
> TEGRA_IO_PADS_UART?

Personally, I think pads and that is purely because it aligns with the
APIs. I think that the APIs names, tegra_io_pads_xxx() should be
consistent with the enum naming.

>>>>> +};
>>>>> +
>>>>> +/* tegra_io_pads_source_voltage: The voltage level of IO rails which
>>>>> source
>>>>> + *                 the IO pads.
>>>>> + */
>>>>> +enum tegra_io_pads_source_voltage {
>>>>> +    TEGRA_IO_PADS_SOURCE_VOLTAGE_1800000UV,
>>>>> +    TEGRA_IO_PADS_SOURCE_VOLTAGE_3300000UV,
>>>>> +};
>>>> Nit I wonder if we can make this shorter ...
>>>>
>>>> enum tegra_io_pads_vconf {
>>>>      TEGRA_IO_PADS_VCONF_1V8,
>>>>      TEGRA_IO_PADS_VCONF_3V3,
>>> This looks good but for voltage and current, unit is used uV/uV across
>>> the system. So wanted to have same unit.
>> Now it is an enum does it matter? Or maybe just have ...
>>
>> enum tegra_io_pads_vconf {
>>     TEGRA_IO_PADS_1800000UV,
>>     TEGRA_IO_PADS_3300000UV,
>> };
>>
> 
> OK, TEGRA_IO_PADS_VCONF_1800000UV and TEGRA_IO_PADS_VCONF_3300000UV.
> Fine?

Fine :-)

Jon

Thread

[PATCH V4 0/3] soc/tegra: Add support for IO pads power and voltage control Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
  [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
    Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-06 16:40 +0200
      Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 17:50 +0200
        Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-08 14:20 +0200
          Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-11 15:50 +0200
            Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-11 17:40 +0200
              Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-11 19:40 +0200
                Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power  state and voltage Jon Hunter <jonathanh@nvidia.com> - 2016-05-11 22:00 +0200
  [PATCH V4 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
    Re: [PATCH V4 2/3] soc/tegra: pmc: Correct type of variable for  tegra_pmc_readl() Jon Hunter <jonathanh@nvidia.com> - 2016-05-06 16:20 +0200
  [PATCH V4 1/3] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-06 13:00 +0200
    Re: [PATCH V4 1/3] soc/tegra: pmc: Use BIT macro for register field  definition Jon Hunter <jonathanh@nvidia.com> - 2016-05-06 16:20 +0200

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