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Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

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On Saturday 16 April 2016 12:00 AM, Jon Hunter wrote:
> On 15/04/16 18:49, Laxman Dewangan wrote:
>> On Friday 15 April 2016 11:14 PM, Jon Hunter wrote:
>>> On 15/04/16 17:41, Laxman Dewangan wrote:
>>>> On Friday 15 April 2016 09:15 PM, Jon Hunter wrote:
>>>>> On 15/04/16 16:14, Laxman Dewangan wrote:
>>>>>> I used pins as this is the property from pincon generic so that I can
>>>>>> use the generic implementation.
>>>>>>
>>>>>> Here, I will not go to the pin level control as HW does not support
>>>>>> pin
>>>>>> level control.
>>>>>>
>>>>>> I will say the unit should be interface level. Should we say
>>>>>> IO_GROUP_CSIA, IO_GROUP_CSIB etc?
>>>>> So we need to reflect the hardware in device-tree and although yes the
>>>>> power-down for the CSI_x_xxx pads are all controlled together as a
>>>>> single group, it does not feel right that we add a pseudo pin called
>>>>> csix to represent these.
>>>>>
>>>>> The CSI_x_xxx pads are already in device-tree and so why not add a
>>>>> property to each of these pads which has the IO rail information for
>>>>> power-down and voltage-select?
>>>> Which dt binding docs have these?
>>>> I looked for nvidia,tegra210-pinmux.txt and not able to find csi_xxx.
>>> For CSI you are right they are not included by the current DT binding
>>> docs, however, the sdmmc1/3 pads are. So that makes things a bit more
>>> messy as some are and some are not.
>> Yaah and so lets have the names in new dt files. Names may be same but
>> define all possible names f groups in dt binding and need not to refer
>> from other file which does not have all.
> I still do not like that. In the case of sdmmc we now have two pinctrl
> drivers to deal with for a single set of pins. That does not seem
> correct IMO.

We are ending two drivers because of the HW blocks. Pins interface and 
pad control are seen two different blocks.

Do you want to add the IO group names also in existing pin control 
driver and the new property, power-enable/disable and 
power-source-voltage belongs to these new io group names.

In this way we will have single driver. We need to see how we can 
support group/pins together.


>
>
>> But interfaces are complex. As a client, it is easy to say power down
>> SDMMC1 IO interface rather than saying power down 10 pins (names) of
>> that group.
> Right and like I said, we could always look up the IO rail from the pins
> associated once at probe time and then control it from there.

I did not get it fully. Can you please help on this using some psuedo 
code and dt property.

For  init, we can pass the regulator handle of the supply to this driver 
and during probe, it can get the voltage from regulator call and then 
set 1.8V or 3.3V. So we need to provide regulator handle from DT instead 
of voltage for probe configuration. Is this what you mean?

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[PATCH 0/7] pinctrl: soc/tegra: Add support to configure IO rail voltage and pad power states Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
  [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
    Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
      Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 19:20 +0200
        Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 20:10 +0200
        Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Jon Hunter <jonathanh@nvidia.com> - 2016-04-12 20:10 +0200
  [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
    Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-13 11:10 +0200
      Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-13 11:20 +0200
        Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-13 11:40 +0200
    Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 16:20 +0200
      Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 16:30 +0200
        Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 17:20 +0200
          Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 17:30 +0200
            Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 17:50 +0200
              Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 19:00 +0200
                Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 19:50 +0200
                Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 20:10 +0200
                Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 20:40 +0200
                Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 21:00 +0200
    Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Stephen Warren <swarren@wwwdotorg.org> - 2016-04-15 18:40 +0200
      Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 18:50 +0200
  [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
    Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 10:10 +0200
      Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 11:00 +0200
        Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 11:30 +0200
          Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 12:10 +0200
            Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 13:20 +0200
              Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 14:00 +0200
                Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 16:10 +0200
                Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 16:20 +0200
                Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-19 12:10 +0200
                Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-26 15:50 +0200
                Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Stephen Warren <swarren@wwwdotorg.org> - 2016-04-26 17:40 +0200
        Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Stephen Warren <swarren@wwwdotorg.org> - 2016-04-15 18:40 +0200
  [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
    Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field  definition Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
      Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field  definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 19:10 +0200
      Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 09:50 +0200

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